Semiconductor memory and method of saving energy of the memory
AssigneeNEC Corporation
InventorNaohisa Nishioka
Life of this patent
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Abstract
In an array of memory cells, multiple prechargers are respectively connected to bit-line pairs of the array. Near-end balancers and far-end balancers are connected to opposite ends of the bit-line pairs. During a read mode of the memory, the prechargers and both near-end and far-end balancers are activated. For power savings purposes, during a write mode the prechargers and the far-end balancers remain inactive and the near-end balancers are activated.
Claims9
A semiconductor memory comprising an array of memory cells, a plurality of bit-line pairs to which the memory cells of said array are connected, and a plurality of prechargers respectively connected to said bit-line pairs, characterized in that said prechargers are active during a read mode of the memory and remain inactive during a write mode of the memory
A semiconductor memory comprising:
- an array of memory cells;
- a plurality of bit-line pairs to which the memory cells of said array are connected;
- a plurality of prechargers respectively connected to said bit-line pairs;
- and
- control circuitry for supplying energy to said prechargers for charging said bit-line pairs exclusively during a read mode of said memory.
A method of saving energy consumption of a semiconductor memory comprising an array of memory cells, a plurality of bit-line pairs to which the memory cells of said array are connected, and a plurality of prechargers respectively connected to said bit-line pairs, the method comprising the step of supplying energy to said prechargers exclusively during a read mode of the memory.
Dependencies are inferred from the claim text.