US 2001/0026481 A1Published application

Method and apparatus for repairing defective columns of memory cells

AssigneeMicron Technology, Inc.

InventorBrian M. Shirley

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Abstract

A pair of coupling transistors are connected in series with isolation transistors in each of a plurality of column node circuits coupled to first and second arrays of memory cells arranged in rows and columns. The coupling transistors for the complimentary digit lines in each column node circuit are rendered non-conductive in the event memory cells connected to the coupling transistors through digit lines of the first and second array are defective. As a result, defective memory cells in the first and second arrays are isolated from sense amplifiers in the column node circuits so that the sense amplifiers cannot affect non-defective memory cells.

Claims40

Dependent claims

A memory device, comprising

a first array of memory cells arranged in rows and columns, the first array including at least one redundant column of memory cells;
a control circuit structured to provide control signals for controlling the operation of the memory device responsive to command signals received by the memory device;
a data path circuit structured to couple data between the first array and an externally accessible data bus, the data path circuit including at least one pair of complimentary input/output lines;
a row address decoder decoding row addresses received by the memory device and activating a row of memory cells corresponding to the row address in the first array;
a plurality of column node circuits each including at least one pair of complimentary digit lines, each of the column node circuits comprising:
a sense amplifier coupled between each pair of the complimentary digit lines of the column node circuit;
an equilibration circuit coupled between each pair of the complimentary digit lines of the column node circuit;
and
an input/output circuit coupled to each pair of the complimentary digit lines of the column node circuit, the input/output circuit being structured to couple each pair of complimentary digit lines of the column node circuit to a respective pair of complimentary input/output lines responsive to a column enable signal;
a column address decoder decoding column addresses received by the memory device and to generate a plurality of the column enable signals, the column address decoder generating at least one of the column enable signals responsive to each of the column addresses;
a pair of first coupling switches selectively coupling each pair of complimentary digit lines in each column node circuit to a pair of complimentary digit lines for a respective column in the first array, the first coupling switches having a conductive state determined by a respective column node disable signal;
a second pair of coupling switches selectively coupling each pair of complimentary digit lines in each column node circuit to a pair of complimentary digit lines for a respective column in the second array, the coupling switches having a conductive state determined by the respective column node disable signal;
and
a redundant column control circuit applying a respective column node disable signal to the first coupling switches coupled to each of the column node circuits, each of the redundant column disable signals causing the first coupling switches coupled to the respective column node circuits to be non-conductive responsive to a redundant column of memory cells being substituted for the column of memory cells to which the column node circuit is coupled.

11 more elements

A column circuit adapted for coupling to a first array of memory cells arranged in rows and columns, the column circuit comprising:

a plurality of column node circuits each including at least one pair of complimentary digit lines, each of the column node circuits comprising:
a sense amplifier coupled between each pair of the complimentary digit lines of the column node circuit;
an equilibration circuit coupled between each pair of the complimentary digit lines of the column node circuit;
and
an input/output circuit coupled to each pair of the complimentary digit lines of the column node circuit, the input/output circuit being structured to couple the pair of complimentary digit lines of the column node circuit to a pair of complimentary input/output lines, respectively, responsive to a column enable signal;
a pair of first coupling switches selectively coupling each pair of the complimentary digit lines in each column node circuit to respective pairs of complimentary digit lines in the first array, the switches having a conductive state determined by a respective column node disable signal;
and
a redundant column control circuit applying respective column node disable signals to the first coupling switches in each of the column node circuit, each of the redundant column disable signals causing the first coupling switches coupled to the respective column node circuits to be non-conductive responsive to a redundant column of memory cells being substituted for the column of memory cells to which the column node circuit is coupled.

5 more elements

A computer system, comprising:

a processor having a processor bus;
an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
and
a memory device, comprising
a first array of memory cells arranged in rows and columns, the first array including at least one redundant column of memory cells;
a control circuit structured to provide control signals for controlling the operation of the memory device responsive to command signals received by the memory device;
a data path circuit structured to couple data between the first array and an externally accessible data bus, the data path circuit including at least one pair of complimentary input/output lines;
a row address decoder decoding row addresses received by the memory device and activating a row of memory cells corresponding to the row address in the first array;
a plurality of column node circuits each including at least one pair of complimentary digit lines, each of the column node circuits comprising:
a sense amplifier coupled between each pair of the complimentary digit lines of the column node circuit;
an equilibration circuit coupled between each pair of the complimentary digit lines of the column node circuit;
and
an input/output circuit coupled to each pair of the complimentary digit lines of the column node circuit, the input/output circuit being structured to couple each pair of complimentary digit lines of the column node circuit to a respective pair of complimentary input/output lines responsive to a column enable signal;
a column address decoder decoding column addresses received by the memory device and to generate a plurality of the column enable signals, the column address decoder generating at least one of the column enable signals responsive to each of the column addresses;
pairs of first coupling switches selectively coupling each pair of complimentary digit lines in each column node circuit to a pair of complimentary digit lines for a respective column in the first array, the first coupling switches having a conductive state determined by a respective column node disable signal;
a second pair of coupling switches selectively coupling each pair of complimentary digit lines in each column node circuit to a pair of complimentary digit lines for a respective column in the second array, the coupling switches having a conductive state determined by the respective column node disable signal;
and
a redundant column control circuit applying a respective column node disable signal to the first coupling switches coupled to each of the column node circuits, each of the redundant column disable signals causing the first coupling switches coupled to the respective column node circuits to be nonconductive responsive to a redundant column of memory cells being substituted for the column of memory cells to which the column node circuit is coupled.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/764,952Filed 16 Jan 2001
Priority: 15 Jul 1999
Published: 4 Oct 2001
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G11C 29/83
Using programmable devices: with reduced power consumption
G11C 29/832
With reduced power consumption: with disconnection of faulty elements
G11C
Static stores

Family

Application09/353,575Continuation · filed 15 Jul 1999
Application09/764,952Continuation · filed 16 Jan 2001
US 6,185,136 B2Related patent
US 6,366,509 B2Related patent
US 2001/0026481 A1This patent

From the US filing history. Foreign family members aren’t listed.

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