Multi-level flash EEPROM cell and method of manufacture thereof

A multi-level flash EEPROM cell, comprising:

• a tunnel oxide layer over a silicon substrate;
• a floating gate over the tunnel oxide layer and electrically isolated from the silicon substrate;
• a dielectric layer over the floating gate;
• first and second control gates at least partially over the dielectric layer and at least partially laterally positioned with respect to one another, said first and second control gates electrically isolated from the floating gate;
• and
• a source and a drain in the substrate, each having a sidewall aligned with a respective one of a pair of sidewalls of the second control gate,
• wherein the floating gate is programmable through a thermion implantation process using a voltage difference between the source and drain, and is erasable by a F-N tunneling process using a voltage difference between the first and second control gates and the drain.

A method for manufacturing a flash EEPROM cell, comprising the steps of:

• forming a tunnel oxide layer over a silicon substrate;
• forming a floating gate by depositing a polysilicon layer over the tunnel oxide layer;
• forming a first dielectric layer over the floating gate;
• forming a first control gate by depositing a polysilicon layer over the first dielectric layer;
• forming a second dielectric layer covering the first control gate;
• forming a second control gate by depositing a polysilicon layer over the second dielectric layer;
• and
• forming a source and a drain in the silicon substrate by ion implantation with a self-aligned etching technique.