US 2001/0026476 A1Published application

Redundancy architecture for an interleaved memory

AssigneeSTMicroelectronics S.r.l.

InventorsLuca Giuseppe De Ambroggi, Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Promod Kumar

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Abstract

A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each semi-array is organized into rows and columns. The redundancy architecture includes a number of packets each including redundancy columns. The packets are divided into two subsets of packets. Each packet is addressable independently from the other by respective address circuits. Each packet also provides redundancy columns exclusively for a respective semi-array.

Claims2

Dependent claims

A redundancy architecture for a memory wherein the array of memory cells is divided in at least a pair of banks or semiarrays (EVEN_BANK, ODD_BANK) singularly addressable (ADDR_latch_E, ADDR_latch_o), organized in rows and columns;

the architecture comprising a certain number of packets each composed of a certain number of redundancy columns of cells (REDUNDANCY), characterized in that
said number of packets (REDUNDANCY) is divided into two subsets of packets (REDUNDANCY_EVEN, REDUNDANCY_ODD), each one being addressable independently from the other by way of respective address circuits and providing redundancy columns of cells exclusively for a respective bank or semiarray (EVEN_BANK, ODD_BANK).

Dependencies are inferred from the claim text.