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US 2001/0026473 A1Published application
Semiconductor memory apparatus that can surely attain discharge operation while reducing discharge period when reading operation is done
AssigneeNEC Corporation
InventorYuuichi Sano
Life of this patent
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Abstract
A semiconductor memory apparatus, includes a plurality of memory cells (MC1˜MC4); and a write circuit (44). The write circuit (44) performs a writing operation on the memory cell (MC1). A first voltage is supplied to the write circuit (44) when the writing operation is performed on the memory cell (MC1). A second voltage equal to or lower than the first voltage is supplied to the write circuit (44) when a reading operation is performed on the memory cell (MC1).
Claims20
A semiconductor memory apparatus, comprising:
- a plurality of memory cells;
- and
- a write circuit performing a writing operation on said memory cell, and
- wherein a first voltage is supplied to said write circuit when said writing operation is performed on said memory cell, and
- wherein a second voltage equal to or lower than said first voltage is supplied to said write circuit when a reading operation is performed on said memory cell.
2 more elements
A semiconductor memory apparatus, comprising:
- a plurality of memory cells connected to a plurality of bit lines;
- and
- a write circuit performing a writing operation on said memory cell, and
- wherein a specific voltage is supplied to said write circuit when a reading operation is performed on said memory cell, said specific voltage being equal to or lower than a voltage of said bit line selected when said reading operation is performed.
1 more element
A semiconductor memory apparatus, comprising:
- a plurality of memory cells;
- a plurality of bit lines connected to said plurality of memory cells;
- a write circuit connected to said plurality of bit lines;
- and
- an N-channel transistor for connecting a first power supply to said write circuit when a first operation is performed and for connecting a second power supply different from said first power supply to said write circuit when a second operation different from said first operation is performed.
2 more elements
Dependencies are inferred from the claim text.