Circuit design apparatus, circuit design method, circuit design program, and semiconductor intergrated circuit fabrication method
AssigneeKabushiki Kaisha Toshiba
InventorsItaru Yamazaki, Nobuyuki Ikumi
Life of this patent
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Abstract
In a circuit design method, an arrangement/wiring section (112) determines an arrangement and wiring of logical blocks (40a, 40b, 40c, 40d) so that delay limitation information about input signals supplied to the logical blocks (40a, 40b, 40c, 40d) and limitation conditions about a difference of delay times among a pre-charge control signal (ck0, ck1, ck2) supplied to the corresponding logical block (40a, 40b, 40c, 40d) and the input signals are satisfied.
Claims19
A circuit design apparatus for determining an arrangement and wiring of logical blocks in a circuit by using circuit design information, comprising an arrangement/wiring section for determining an arrangement and wiring of the logical blocks in the circuit so that both delay limitation information about input signals to be supplied to the logical blocks and limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals are satisfied.
A circuit design method of determining an arrangement and wiring of logical blocks in a circuit by using circuit design information, comprising the steps of:
- inputting delay limitation information about input signals to be supplied to the logical blocks and limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals;
- and
- determining the arrangement and the wiring of the logical blocks in the circuit so that both the delay limitation information and the limitation conditions are satisfied.
A circuit design program to be used for executing a circuit design method of determining an arrangement and wiring of logical blocks in a circuit by using circuit design information, comprising the programs of:
- inputting delay limitation information about input signals to be supplied to the logical blocks and limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals;
- and
- determining the arrangement and the wiring of the logical blocks in the circuit so that both the delay limitation information and the limitation conditions are satisfied.
A semiconductor integrated circuit fabrication method of fabricating a semiconductor integrated circuit, comprising the steps of:
- inputting circuit design information obtained by determining an arrangement and wiring of logical blocks so that the following delay limitation information and limitation conditions are satisfied:
- the delay limitation information about input signals to be supplied to the logical blocks;
- and
- the limitation conditions about a difference of delay times among a pre-charge control signal to be supplied to the corresponding logical block and the input signals;
- and
- fabricating the semiconductor integrated circuit by performing the arrangement and wiring of the logical blocks based on the circuit design information.
Dependencies are inferred from the claim text.