Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency

A method for increasing communication efficiency in a multi-processor system, comprising:

• generating, at a level one cache in a processor, a first command requiring a reservation;
• checking said reservation prior to placing said first command on a system bus, said system bus providing communication between processors in said multi-processor system;
• and
• converting said first command into a second command, which does not require a reservation, when said checking step indicates that said reservation for said first command has been lost.

A method for increasing communication efficiency in a multi-processor system, comprising:

• storing a non-exclusive command associated with a real address in a transition cache of a processor;
• snooping, at said processor, a command on a system bus providing communication between processors in said multi-processor system, said snooped command being associated with said real address;
• determining, at said transition cache, whether data has started to arrive at said transition cache in response to said non-exclusive command;
• and
• generating a snoop response at said transition cache to said snooped command based on a result of said determining step.

A method for increasing communication efficiency in a multi-processor system, comprising:

• receiving, at a processor, a first command on a system bus, said system bus providing communication between processors in said multi-processor system, said first command requesting a cache line;
• transferring said requested cache line from a cache associated with said processor to a transition cache in said processor as part of a response to said first command;
• updating a memory coherency image state associated with said cache line in each cache associated with said processor that stores said cache line;
• snooping a system response to said first command on said system bus;
• and
• processing said requested cache line at said processor based on said system response.

A multi-processor system, comprising:

• at least first and second processors;
• a system bus providing communication between said first and second processors;
• a bus arbiter generating system responses to commands on said system bus;
• and wherein
• said first processor has at least one level of cache associated therewith, a system bus controller controlling communication between said first processor and said system bus, and a transition cache serving as an interface between each level of cache and said system bus controller;
• one of said levels of cache associated with said first processor stores a cache line having a memory coherency image state indicating that said cache line includes modified data, and generates a castback command and transfers said castback command and a copy of said cache line to said transition cache when said first processor snoops a first command on said system bus that requests invalidation of said cache line;
• and
• each level of cache associated with said first processor that stores said cache line invalidates said cache line prior to said first processor snooping a system response to said first command.

A multi-processor system, comprising:

• at least first and second processors;
• a system bus providing communication between said first and second processors;
• a bus arbiter generating system responses to commands on said system bus;
• and wherein
• said first processor includes at least a level one cache, a system bus controller controlling communication between said first processor and said system bus, and a transition cache controlling and tracking communication between each level of cache and said system bus controller;
• and
• said system bus controller checks a reservation of a first command, which requires a reservation, generated by said level one cache prior to placing said first command on said system bus, and converts said first command into a second command, which does not require a reservation, when said reservation for said first command has been lost.

A multi-processor system, comprising:

• at least first and second processors;
• a system bus providing communication between said first and second processors;
• a bus arbiter generating system responses to commands on said system bus;
• and wherein
• said first processor includes at least one level of cache associated therewith, a system bus controller controlling communication between said first processor and said system bus, and a transition cache controlling and tracking communication between each level of cache and said system bus controller;
• and
• said transition cache determines whether data has started to arrive at said transition cache in response to a non-exclusive command, which is associated with a real address, stored therein when said first processor snoops a command on said system bus which is associated with said real address, and generates a snoop response to said snooped command based on said determination.

A multi-processor system, comprising:

• at least first and second processors;
• a system bus providing communication between said first and second processors;
• a bus arbiter generating system responses to commands on said system bus;
• and wherein
• said first processor has at least one cache associated therewith, a system bus controller controlling communication between said first processor and said system bus, and a transition cache controlling and tracking communication between each cache and said system bus controller;
• said first processor receives a first command on said system bus requesting a cache line;
• one of said caches associated with said first processor that stores said requested cache line copies said requested cache line to said transition cache as part of a response to said first command;
• each cache associated with said first processor, that stores said requested cache line, updates a memory coherency image state associated with said requested cache line prior to snooping a system response to said first command;
• and
• said first processor snoops said system response on said system bus to said first command, and processes said requested cache line based on said system response.