Write cache circuit, recording apparatus with write cache circuit, and write cache method
AssigneeSanyo Electric Co., Ltd.
InventorsMasato Fuma, Miyuki Okamoto
Life of this patent
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Abstract
User data transmitted from the host side is first stored in write cache regions of an SDRAM 12 on the basis of an error correction process. When executing an ECC.EDC encode process of adding redundancy data such as an error correction code to the stored user data on the basis of the error correction processing, an encode region of SDRAM 12 is used. The data subjected to the ECC.EDC encode process is sequentially read out from encode region to be modulated and then written onto a disk.
Claims15
A write cache circuit in a recording apparatus recording data transferred from a host on a recording medium with redundancy data for an error correction process added, said write cache circuit comprising:
- a random access memory including a host write region and an encode work region,
- a write circuit writing said data transferred from said host into said host write region on the basis of an error correction block,
- a circuit transferring said data on the basis of the error correction block written in said host write region into said encode work region, and reading data out from said encode work region for a process of adding said redundancy data, or writing data obtained as a result of said process of adding redundancy data back into said encode work region, and
- a read circuit reading out data already added with said redundancy data from the data in said encode work region for recording on said recording medium.
A recording apparatus recording data transferred from a host on a recording medium with redundancy data for an error correction process added, said recording apparatus comprising:
- an encoder adding said redundancy data,
- a write cache circuit, and
- a record processing circuit modulating data added with said redundancy data for recording on said recording medium,
- wherein said write cache circuit comprises
- a random access memory including a host write region and an encode work region,
- a write circuit writing said data transferred from said host into said host write region on the basis of an error correction block,
- a circuit transferring said data on the basis of the error correction block written in said host write region to said encode work region, and providing data from said encode work region to said encoder, or writing data received from said encoder back into said encode work region, and
- a read circuit reading out data already added with said redundancy data from the data in said encode work region and providing the read data to said record processing circuit.
A write cache method of a recording apparatus including a random access memory having a host write region and an encode work region, and recording data transferred from a host on a recording medium with redundancy data for an error correction process added, said write cache method comprising the steps of:
- writing said data transferred from said host into said host write region on the basis of an error correction block,
- transferring said data on the basis of the error correction block written in said host write region to said encode work region, and reading out 10 data from said encode work region for a process of adding said redundancy data, or writing data obtained as a result of said process of adding redundancy data back into said encode work region, and
- reading out data already added with redundancy data from the data in said encode work region for recording on said recording medium.
Dependencies are inferred from the claim text.