Method and apparatus for generating a discretely variable capacitance for synthesizing high-frequency signals for wireless communications

Abstract

A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, a plurality of connected capacitor circuits for the discretely variable capacitance are disclosed each having a first switch that selectively couples a capacitor between two nodes. A multiple-bit digital control signal is also disclosed that couples to the control nodes of the plurality of switches to select an overall capacitance for the discretely variable capacitance circuit, with at least two of the capacitors have different capacitance values with respect to each other.

Dependencies are inferred from the claim text.