Sense amplifier circuit for use in a semiconductor memory device

A semiconductor memory device comprising at least one pair of bit lines;

• a pair of input/output (I/O) lines corresponding to the bit lines of the pair;
• and an I/O sense amplifier circuit coupled to the I/O lines of the pair, wherein the I/O sense amplifier circuit comprises:
• a current sense amplifier for sensing a current differential between the input/output lines to output differential signals;
• a voltage sense amplifier for amplifying voltages of the differential signals outputted from the current sense amplifier;
• and
• a latch circuit for latching the differential signals from the voltage sense amplifier in response to a latch signal, wherein the latch circuit includes a first differential amplifier for receiving the differential signals from the voltage sense amplifier;
• a second differential amplifier for receiving the differential signals from the voltage sense amplifier;
• and gain control means coupled between output terminals of the first and second differential amplifiers, the gain control means setting a voltage gain of each of the first and second differential amplifiers that varies in response to the latch signal.