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US 2001/0024394 A1Published application
Split gate type flash memory
AssigneeSamsung Electronics Co., Ltd.
InventorsByung-Ki Kim, Won-Il Ryu
Life of this patent
Estimating the term…
Abstract
A split gate type flash memory having an active region that improves an endurance characteristic along with program/erase efficiency, wherein the split gate type flash memory provides for improvement in the endurance characteristic and program/erase efficiency by making the width of an active region in a portion in which a source is overlapped by a floating gate as large as possible.
Claims3
A split gate type flash memory comprising:
- a substrate;
- a source, a drain and a channel provided over the substrate;
- a gate insulating layer provided on the source, the drain and the channel;
- a floating gate stacked on the gate insulating layer overlying the source and the channel;
- an intergate insulating layer and a tunnel insulating layer stacked on the top and the side of the floating gate, respectively;
- and
- a control gate stacked on the intergate insulating layer, the tunnel insulating layer and the gate insulating layer,
- wherein an active region is formed so that the width of the channel under the floating gate is larger than the width of the channel under the control gate.
5 more elements
A split gate type flash memory comprising:
- a substrate;
- a source, a drain and a channel provided over the substrate;
- a gate insulating layer provided on the source, the drain and the channel;
- a floating gate stacked on the gate insulating layer overlying the source and the channel;
- an intergate insulating layer and a tunnel insulating layer stacked on the top and the side of the floating gate, respectively;
- and
- a control gate stacked on the intergate insulating layer, the tunnel insulating layer and the gate insulating layer,
- wherein an active region is formed so that the source underlying the floating gate is larger than the width of the channel under the control gate.
5 more elements
A split gate type flash memory comprising:
- a substrate;
- a source, a drain and a channel provided over the substrate;
- a gate insulating layer provided on the source, the drain and the channel;
- a floating gate stacked on the gate insulating layer overlying the source and channel;
- an intergate insulating layer and a tunnel insulating layer stacked on the top and side of the floating gate, respectively;
- and
- a control gate stacked on the intergate insulating layer, the tunnel insulating layer, and the gate insulating layer,
- wherein an active region is formed so that the width of the channel under the floating gate is larger than the width of the channel under the control gate, and the source underlying the floating gate is larger than the width of the channel under the control gate.
5 more elements
Dependencies are inferred from the claim text.