Back to results
US 2001/0024392 A1Published application
Method of testing a memory cell having a floating gate
AssigneeInfineon Technologies AG
InventorsJens Lupke, Peter Pochmuller
Life of this patent
Estimating the term…
Abstract
The memory cells with floating gates are tested by applying voltage surges to the source or the drain of a selection transistor.
Claims7
A memory cell testing method, which comprises:
- providing a memory cell with a selection transistor having a floating gate disposed between a bit line and ground, and a blocking transistor connected between the floating gate of the selection transistor and a data line and having a gate connected to a word line;
- in a test mode, applying voltage surges to one of the source, the drain, and a substrate of the selection transistor for generating disturbing couplings to the floating gate.
A testing configuration for testing a memory cell having a selection transistor with source, a drain, and a floating gate disposed between a bit line and ground, the testing configuration comprising:
- two MOS transistors of mutually different channel types connected in series and forming a connecting node;
- said MOS transistors having gates and having source-drain paths connected between two potentials;
- and
- said connecting node between said MOS transistors being connected to one of the source and the drain of the selection transistor;
- and
- an inverter connected to said gates of said MOS transistors for receiving test mode signals.
3 more elements
Dependencies are inferred from the claim text.