Semiconductor memory device and method of testing the same

A method of testing a semiconductor memory device comprising an array of regular memory cells and an array of redundancy memory cells to be used for relief by means of a built-in type test circuit, said method comprising:

• a step of performing a sequence of changing the addresses on the basis of a unit of redundancy, testing the addresses of the unit of redundancy to determine whether faulty memory cells are detected or not, and relieving the faulty memory cells by using the redundancy memory cells;
• inputting redundant information to said register;
• testing again said addresses;
• continuing the test and the relief operation until no faulty memory cells are detected;
• and performing the test and the relief operation to next and succeeding addresses of the unit of redundancy after the elimination of faulty memory cells;
• and
• a step of outputting a pass signal at the time of completion of the test to the last addresses of the unit of redundancy, while outputting a fail signal to end the test operation in the case of consuming all the redundancy cells before outputting a pass signal.

A method of testing a semiconductor memory device comprising an X, Y two-dimensional address space and two-dimensional redundancy memory cells by means of a built-in type test circuit, said method performs the sequence including the steps of:

• changing the X addresses on the basis of a unit of redundancy, while fixing the Y address, and testing the X addresses of the unit of redundancy, while fixing the Y address to determine whether faulty memory cells are detected or not;
• using the Y redundancy memory cells when the faulty memory cells are not relieved by using the X redundancy cells alone, while using the X redundancy memory cells when the faulty memory cells are relieved by using the X redundancy cells alone;
• testing again said X addresses;
• continuing the test and the relief operation until no faulty memory cells are detected;
• performing the test and the relief operation to next and succeeding x addresses of the unit of redundancy after the elimination of faulty memory cells;
• shifting the Y address and performing a similar test in the X direction;
• and
• outputting a pass signal at the time of completion of the test of the last address of the unit of redundancy, while outputting a fail signal to end the test operation in the case of consuming all the redundancy cells before outputting a pass signal.