US 2001/0024204 A1 · Method and apparatus for comparing frequently the phase of a target clock signal with the phase of a reference clock signal enabling quick synchronization

Abstract

A phase comparator circuit which can compare the phase of a target clock signal with the phase of a reference clock signal with a short comparison cycle. An auxiliary waveform representative of the incremental phase of each of the reference and target clock signals may be generated, and samples on the auxiliary waveforms may be compared to determine the relative phase. The result of the comparison can be used to adjust of the phase of the target clock signal. As several samples can be taken on the auxiliary waveforms, the present invention enables frequent phase comparisons. The frequent comparisons may enable the target clock signal to be synchronized quickly with the reference clock signal. The invention has particular application in display units using phase lock loops (PLLs).

Claims28

Dependent claims

A method of generating a target clock signal synchronized with a reference clock signal, said method comprising the steps of:

(a) generating a first waveform representing the incremental phase advancement of said reference clock signal;
(b) generating a second waveform representing the incremental phase advancement of said target clock signal;
(c) selecting a first sample on said first waveform;
(d) selecting a second sample on said second waveform;
(e) comparing said first sample with said second sample;
and
(f) adjusting the phase of said target clock signal according to the result of step (e) to generate said target clock signal synchronized with said reference clock signal.

4 more elements

A clock generation circuit for generating a target clock signal synchronized with a reference clock signal, said circuit comprising:

a first circuit for generating a first waveform representing the incremental phase advancement of said reference clock signal;
a second circuit for generating a second waveform representing the incremental phase advancement of said target clock signal;
a comparison circuit coupled to said first circuit and said second circuit, said comparison circuit for comparing said first waveform and said second waveform;
a phase-lock loop (PLL) coupled to said comparison circuit, said PLL for receiving the result of said comparison, and adjusting the phase of said target clock signal according to the result of to synchronize said target clock signal with said reference clock signal.

1 more element

Dependencies are inferred from the claim text.

Method and apparatus for comparing frequently the phase of a target clock signal with the phase of a reference clock signal enabling quick synchronization

Life of this patent

Method and apparatus for comparing frequently the phase of a target clock signal with the phase of a reference clock signal enabling quick synchronization

Life of this patent

Abstract

Claims28