Semiconductor integrated circuit compensating variations of delay time
AssigneeNEC Corporation
InventorTakashi Yamada
Life of this patent
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Abstract
A semiconductor device includes a first circuit and a second circuit cascaded therefrom, a pattern examination section for examining the input signal pattern for the first circuit to estimate a delay in the first circuit, a delay control block for controlling an internal source potential based on the estimated delay for controlling the source potential for the second circuit so that the signal delay from the second circuit has small variations of delay time. The integrated circuit can be formed on a reasonable specification, and achieves a lower dissipation and a higher reliability.
Claims12
A semiconductor integrated circuit comprising an input section for receiving an input signal pattern, an internal circuit for operating based on said input signal pattern for a specific function, a pattern examination block for examining said input signal pattern to estimate a delay time in said internal circuit and deliver a delay control signal based on said estimated delay time, and a delay control block for controlling the delay time in said internal circuit based on said delay control signal.
Dependencies are inferred from the claim text.