Method for manufacturing semiconductor device and insulated gate type power transistor

An insulated gate type power transistor comprising:

• a semiconductor substrate composed of a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type disposed on the first semiconductor region, and a third semiconductor region of the first conductivity type disposed on the second semiconductor region and forming a main surface of the semiconductor substrate;
• and
• a gate electrode disposed in a trench via a gate insulating film, thereby forming a MOS structure in which a channel region is provided on a surface of the second semiconductor region opposed to the gate electrode on a side wall of the trench with the gate insulating film interposed therebetween, wherein:
• the trench has a straight portion extending in the second and third semiconductor regions from the main surface in a vertical direction vertical to the main surface so as to reach the first semiconductor region, and an expanding portion expanding from a bottom end of the straight portion in a lateral direction parallel to the main surface and forming a bottom portion of the trench, an entirety of the expanding portion being contained in the first semiconductor region.