Structure for improving static refresh and its method of manufacture

A method of forming a metal oxide semiconductor field effect transistor comprising the steps of:

• providing a gate structure on a surface of a semiconductor substrate;
• implanting a dopant within the substrate to form first and second diffusion regions underneath the surface of the substrate;
• oxidizing sidewalls of the gate structure;
• and
• implanting the dopant within the substrate at locations of the first and second diffusion regions to add additional dopant to the first and second diffusion regions, wherein each diffusion region comprises a first portion having a first dopant concentration and a second portion having a second dopant concentration.

A method of forming a memory array device on a substrate, the device comprising a gate structure provided on a surface of the substrate, said method comprising the steps of:

• blanket ion implanting a dopant at a first energy level and first dose into the substrate to form first and second diffusion regions underneath the surface of the substrate on opposite sides of the gate structure;
• oxidizing sidewalls of the gate structure;
• and
• blanket ion implanting the dopant at a second energy level and second dose into the substrate at locations of the first and second diffusion regions to add additional dopant to the first and second diffusion regions, wherein each diffusion region comprises a first portion having a first dopant concentration and a second portion having a second dopant concentration.

An integrated circuit semiconductor device comprising:

• a substrate having a first surface;
• a gate structure formed on said first surface;
• and
• first and second diffusion regions formed within said substrate on opposite sides of said gate structure, wherein each of said diffusion regions comprise first and second portions respectively having first and second dopant concentrations, which are different and cause each diffusion region to have a graded dopant concentration.

A processor-based system comprising:

• a processor;
• and
• a memory circuit coupled to said processor, said memory circuit comprising:
• a substrate having a first surface;
• a gate structure formed on said first surface;
• and
• first and second diffusion regions formed within said substrate on opposite sides of said gate structure, wherein each of said diffusion regions comprise first and second portions respectively having first and second dopant concentrations, which are different and cause each diffusion region to have a graded dopant concentration.

A processor-based system comprising:

• a processor;
• and
• a memory circuit coupled to said processor, said memory circuit being integrated on a same chip as said processor, said memory circuit comprising:
• a substrate having a first surface;
• a gate structure formed on said first surface;
• and
• first and second diffusion regions formed within said substrate on opposite sides of said gate structure, wherein each of said diffusion regions comprise first and second portions respectively having first and second dopant concentrations, which are different and cause each diffusion region to have a graded dopant concentration.