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US 2001/0023533 A1Published application
Method of increasing package reliability using package lids with plane CTE Gradients
OwnerMark F. Sylvesterinventor
Life of this patent
Estimating the term…
Abstract
A package for mounting an integrated circuit chip includes a body having at least a first region and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region approximately matches the CTE of the integrated circuit chip mounted on the package, and the second region approximates the CTE of the printed wiring board to which the package is mounted.
Claims12
A method of improving reliability for a chip/package system, comprising the steps of:
- forming a package that exhibits first and second discrete coefficients of thermal expansion (CTEs) in first and second discrete regions thereof.
Dependencies are inferred from the claim text.