Reducing waiting time jitter
AssigneeADC Telecommunications, Inc.
InventorMichael J. Rude
Life of this patent
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Abstract
Circuits and methods are described which reduce waiting time jitter at a synchronizer/multiplexer by using a “sub-bit” comparison of a clock associated with an unsynchronized data stream and a clock associated with a synchronized data stream to generate a threshold level for use in determining when to stuff bits into the synchronized data stream. The term “sub-bit” means that the phase difference, as measured by, for example, the location of pointers associated with the two clocks, is precise to a fraction of a bit.
Claims24
A method for reducing waiting time jitter in a system using bit stuffing synchronization, the method comprising:
- receiving an unsynchronized data stream;
- writing the data of the unsynchronized data stream to an elastic store;
- reading the data from the elastic store as part of a synchronized data stream;
- detecting a sub-bit phase difference of clocks associated with the synchronized and unsynchronized data streams;
- filtering the sub-bit phase difference;
- varying a threshold level based on the filtered sub-bit phase difference;
- comparing the clocks associated with the synchronized and unsynchronized data streams with the threshold level;
- and
- controlling the length of frames in the synchronized data stream based on the comparison with the threshold level by selectively stuffing bits into the frames so as to reduce the waiting time jitter.
A method for reducing waiting time jitter in a synchronizer, the method comprising:
- generating a sub-bit phase comparison of read and write clocks used to pass unsynchronized data through an elastic store;
- comparing read and write pointers for the read and write clocks with a threshold level;
- generating a frame of synchronized data from the data in the elastic store with a length that is dependent on the result of comparing the read and write pointers with the threshold level;
- and
- selecting the threshold level used in comparing the read and write pointers based on the generated sub-bit phase comparison so as to reduce waiting time jitter.
A synchronizer circuit, comprising:
- an elastic store that receives an unsynchronized data stream;
- a write clock that controls the writing of data to the elastic store;
- a read clock that controls the reading of data from the elastic store;
- a multiplexer that receives the data read from the elastic store;
- a phase detector that compares the phase of the read and write clocks;
- a threshold generator that generates a variable threshold value based on an output of the phase detector;
- a comparator that compares an output of the phase detector with the threshold value;
- and
- a control logic coupled to the multiplexer that controls the insertion of stuff bits based on the output of the comparator so as to reduce waiting time jitter.
A synchronizer, comprising:
- an elastic store that receives an unsynchronized data stream;
- a multiplexer, coupled to the elastic store, that produces a synchronized data stream from the unsynchronized data stream by the controlled insertion of stuff bits;
- and
- a control circuit that controls the insertion of stuff bits into the synchronized data stream based on a comparison of the phase difference of clocks associated with the synchronized and unsynchronized data streams with a variable threshold level that is generated from a sub-bit phase comparison of clocks associated with the synchronized and unsynchronized data streams so as to reduce waiting time jitter.
A telecommunications network, comprising:
- a synchronizer;
- a desynchronizer;
- a synchronous link coupling the synchronizer to the desynchronizer;
- and
- wherein the synchronizer includes:
- an elastic store that receives an unsynchronized data stream;
- a multiplexer, coupled to the elastic store, that produces a synchronized data stream from the unsynchronized data stream by the controlled insertion of stuff bits;
- and
- a control circuit that controls the insertion of stuff bits into the synchronized data stream based on a comparison of the phase difference of clocks associated with the synchronized and unsynchronized data streams with a variable threshold level that is generated from a sub-bit phase comparison of clocks associated with the synchronized and unsynchronized data streams so as to reduce waiting time jitter.
Dependencies are inferred from the claim text.