Synchronous memory with programmable read latency
AssigneeMicron Technology, Inc.
InventorJ. Thomas Pawlowski
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Abstract
The present invention is directed to a logic circuit for controlling the read latency time of a memory circuit. The logic circuit comprises a first circuit for producing a plurality of values derived from a read enable signal. Each of the values represents the read enable signal delayed by a predetermined period of time. The logic circuit also comprises a second circuit for selecting one of the plurality of values in response to at least one control signal. The selected value enables a read operation of the memory circuit. A method for controlling the read latency time of a memory circuit is also disclosed.
Claims28
A logic circuit for controlling the read latency time of a memory circuit, comprising:
- a first circuit for producing a plurality of values derived from a read enable signal, each value representative of the read enable signal delayed by a predetermined period of time;
- and
- a second circuit for selecting one of said plurality of values in response to at least one control signal to enable a read operation.
A logic circuit for controlling the read latency time of a memory circuit comprising:
- a signal generation circuit for generating a read enable signal;
- a delay circuit for receiving said read enable signal and for producing a plurality of values of said read enable signal each delayed by a predetermined period of time;
- and
- a multiplexer for selecting one of said plurality of values in response to at least one control signal.
In combination, an output stage of a memory circuit and a control logic circuit for controlling its read latency time, said combination comprising:
- a sense amplifier;
- an output register responsive to said sense amplifier;
- an output buffer responsive to said output register;
- a delay circuit for receiving a read enable signal and for producing a plurality of values of the read enable signal each delayed by a predetermined period of time;
- and
- a circuit for selecting one of said plurality of values as a control input to said output register and to said output buffer in response to externally supplied control signals.
A memory circuit, comprising:
- a memory array;
- write control and addressing logic connected to said memory array;
- sense amplifiers connected to said memory array;
- output registers connected to said sense amplifiers;
- and
- read output control logic responsive to a plurality of control signals for controlling the frequency of enablement of said output registers.
A system, comprising:
- a controlling device;
- a memory array;
- write control and addressing logic connected to said memory array;
- sense amplifiers connected to said memory array;
- output registers connected to said sense amplifiers for outputting said read information;
- and
- read output control logic responsive to a plurality of control signals for controlling the frequency of enablement of said output registers.
A method for controlling the read latency time of a memory circuit, comprising the steps of:
- delaying a read enable signal to produce a plurality of values, each value representative of said read enable signal delayed by a predetermined period of time;
- and
- selecting one of said plurality of values in response to at least one control signal, said selected value being used to enable a read operation.
Dependencies are inferred from the claim text.