Circuit and method for timing multi-level non-volatile memories

An electronic multi-level non-volatile memory device integrated in a semiconductor, comprises:

• a cell matrix and associated address, decode, read, write and erase circuitry;
• a dummy path which includes at least one dummy wordline, said dummy wordline being supplied a supply voltage and associated with dummy decode circuitry arranged to receive an ATD signal;
• and
• an auxiliary read timing circuit connected to the dummy path and structured to generate and issue an equalization signal to a sense amplifier placed downstream of the dummy path, wherein the read timing circuit includes;
• a first MOS transistor having a control terminal coupled to the supply voltage, a first conduction terminal coupled to the supply voltage, and a second conduction terminal at which a reference signal is produced;
• and
• means of comparing a potential of the dummy path with a reference signal, so as to generate said equalization signal upon said dummy wordline attaining a potential that is a predetermined percentage of said supply voltage.