Semiconductor memory device and redundancy circuit, and method of increasing redundancy efficiency

A redundancy circuit of a semiconductor memory device that has a plurality of memory cell array blocks respectively including a plurality of partial blocks and at least more than one redundant partial blocks, comprising:

• control signal generators, respectively included for each of the at least more than one redundant partial blocks, that generate a predetermined number of block control signals by dividing the plurality of memory cell array blocks into a predetermined number of groups;
• a predetermined number of defective redundant enable signal generators included for each of the at least more than one redundant partial blocks, that generate a predetermined number of redundant enable signals when defective addresses corresponding to each of the predetermined number of block control signals are input;
• and
• selectors, respectively included for each of the at least more than one redundant partial blocks, that generate each of the predetermined number of redundant enable signals into a select signal that selects the corresponding redundant partial block in response to each of the predetermined number of block control signals.

A redundancy method of a semiconductor memory device which includes a plurality of partial blocks and at least more than one redundant partial blocks respectively as a plurality of memory cell array blocks, a plurality of column select signal lines connected to the plurality of partial blocks, and at least more than one redundant column select signal lines connected to the at least more than one redundant partial blocks, comprising:

• generating a predetermined number of block control signals for each of the at least more than one redundant column select signal lines by dividing the plurality of memory cell array blocks into a predetermined number of groups;
• generating a predetermined number of redundant enable signals for each of the at least more than one redundant column select signal lines, when defective addresses corresponding to each of the predetermined number of block control signals are input;
• and
• generating each of the predetermined number of redundant enable signals into a select signal that selects a corresponding redundant column select signal line in response to each of the predetermined number of block control signals, for each of the at least more than one redundant column select signal lines.