Semiconductor memory device having a page latch circuit and a test method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsJunichiro Noda, Tamio Ikehashi, Kenichi Imamiya
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Abstract
A semiconductor memory device invention having a data latch circuit disclosed in the present invention, comprising a plurality of bit lines to which a reprogramable memory cell is connected, a data bus on which data is transferred, a latch circuit having latching the data transferred on the data bus, a read our circuit connected to the data bus and a data transfer circuit group having an ability to directly transfer the data latched in the latch circuit, to the read our circuit without transferred to the memory cell.
Claims25
A semiconductor memory device having a data latch circuit, comprising:
- a plurality of bit lines to which a reprogramable memory cell is connected;
- a data bus on which data is transferred;
- a latch connected to each of the plurality of bit lines;
- a read our circuit connected to the data bus;
- and
- a data transfer circuit group having an ability to directly transfer the data loaded in the latch circuit, to the read our circuit without transferred to the memory cell.
A semiconductor memory device having a data latch circuit comprising:
- a plurality of bit lines to which a reprogramable memory cell is connected;
- a data bus on which data is transferred;
- a latch circuit having latching the data transferred on the data bus;
- a read our circuit connected to the data bus;
- and
- a data transfer circuit group;
- wherein the data transfer circuit group is controlled so as to transfer the data latched in the latch circuit, to the read our circuit without via the memory cell.
A test method of a semiconductor memory device comprising steps of:
- latching data at a page latch via a data bus on which the data are transferred;
- transferring the data latched in the page latch to a cell matrix for stored the data at a first mode and to a read out circuit at a second mode for testing whether or not an error occurs at a data transfer circuit group including the data bus, the page latch and read out circuit.
Dependencies are inferred from the claim text.