Method and apparatus for reducing induced switching transients

An attenuating circuit adapted to produce an output signal with reduced switching transients, the attenuating circuit comprising:

• a first conductor coupled to a first voltage source, the first conductor having a first inductance;
• a second conductor coupled to a second voltage source, the second conductor having a second inductance;
• a primary circuit coupled to the first conductor at a first location and to the second conductor at a second location, the primary circuit receiving the first voltage source, the second voltage source, and at least one input signal, the primary circuit receiving the first voltage source through the first conductor and the second voltage source through the second conductor, the primary circuit having a first current draw from the first and second conductors responsive to each input signal having a first state and having a second current draw from the first and second conductors responsive to each input signal having a second state, the primary circuit producing a first output signal in response to receiving each input signal;
• a smoothing circuit coupled to the first and second conductor, the smoothing circuit receiving the first voltage source, the second voltage source, and each input signal, the smoothing circuit receiving the first voltage source through the first conductor and the second voltage source through the second conductor, the smoothing circuit having a third current draw from the first and second conductors responsive to each input signal having a first state, and having a fourth current draw from the first and second conductors responsive to each input signal having a second state, the sum of the first and third current draws approximately equaling the sum of the second and fourth current draws.

A dynamic random access memory having an address bus and at least one data bit line, comprising:

• an array of memory cells having a plurality of memory cells arranged in rows and columns, a plurality of row lines, and at least one digitline for each column of memory cells;
• an addressing circuit coupled to the address bus, the addressing circuit adapted to receive row and column addresses on the address bus and activate a corresponding memory cell in the array;
• an output data buffer circuit coupled between the array and the data bit line, the output data buffer circuit adapted to receive a data bit and to transmit the data bit to the data bit line;
• and
• a smoothing circuit having current draw characteristics that are complementary to a memory circuit in the dynamic random access memory, the memory circuit being coupled to a first voltage source through a first conductor having an inductance, the smoothing circuit being coupled to the first voltage source through the first conductor.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a memory device coupled to the processor through the processor bus and having an address bus and a data bit line, the memory device comprising:
• an array of memory cells having a plurality of memory cells arranged in rows and columns, a plurality of row lines, and at least one digitline for each column of memory cells;
• an addressing circuit coupled to the address bus, the addressing circuit adapted to receive row and column addresses on the address bus and activate a corresponding memory cell in the array;
• an output data buffer circuit coupled between the array and the data bit line, the output data buffer circuit adapted to receive a data bit and to transmit the data bit to the data bit line;
• and
• a smoothing circuit having current draw characteristics that are complementary to a memory circuit in the dynamic random access memory, the memory circuit being coupled to a first voltage source through a first conductor having an inductance, the smoothing circuit being coupled to the first voltage source through the first conductor.