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US 2001/0019149 A1Published application
Flash memory device and a fabrication process thereof
AssigneeFujitsu Limited
InventorSATOSHI TAKAHASI
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Abstract
A NOR-type flash memory device includes a source region, a drain region and a source line connecting the source region of a memory cell transistor to an source region of an adjacent memory cell transistor in the form of diffusion regions formed in a substrate, wherein the drain region and the source line are formed simultaneously after the step of forming the source region.
Claims12
A method of fabricating a semiconductor device, said semiconductor device comprising:
- a substrate carrying a field insulation film thereon;
- a tunneling insulation film formed on said substrate so as to cover an active region defined by said field insulation film;
- and a gate structure provided on said tunneling insulation film and including a floating gate electrode formed on said tunneling insulation film, an interlayer insulation film provided on said floating gate electrode and a control electrode formed on said interlayer insulation film, said method comprising the steps of:
- forming a first diffusion region in said active region by conducting a first ion implantation process at a first side of said gate structure;
- exposing, after said step of forming said first diffusion region, a surface of said substrate outside said active region by removing a part of said field insulation film adjacent to said first diffusion region;
- forming a second diffusion region in said active region by conducting a second ion implantation process as a second, opposite side of said gate structure, and concurrently forming a third diffusion region adjacent to said first diffusion region by conducting a third ion implantation process to said exposed surface of said substrate.
3 more elements
A semiconductor device, comprising:
- a substrate;
- a field insulation film formed on said substrate so as to define an active region;
- a gate structure formed on said active region of said substrate, said gate structure including a tunneling insulation film covering said active region, a floating gate electrode provided on said tunneling insulation film, an interlayer insulation film provided on said floating gate electrode, and a control electrode provided on said interlayer insulation film, said gate structure further including a first side wall insulation film on a first side wall of said gate structure and a second side wall insulation film on a second, opposite side wall of said gate structure;
- a first diffusion region formed in said active region of said substrate at a first side of said gate structure, said first diffusion region including an inner region and an outer region surrounding said inner region, said outer region having an impurity concentration level lower than an impurity concentration level of said inner region;
- a second diffusion region formed in said active region of said substrate at a second, opposite side of said gate structure, said second diffusion region having a conductivity type identical with a conductivity type of said first diffusion region;
- a groove formed in said field insulation film adjacent to said inner region of said first diffusion region, said groove exposing a surface of said substrate;
- and
- a third diffusion region formed in said surface of said substrate exposed by said groove, in continuation with said inner region of said first diffusion region, said third diffusion region having a conductivity type identical with said conductivity type of said first and second diffusion regions,
- wherein said second diffusion region and said third diffusion region contain a common impurity element with an identical concentration level.
6 more elements
Dependencies are inferred from the claim text.