Field effect transistor and manufacturing method thereof

A method of manufacturing a field effect transistor which comprises the steps of:

• forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a contact layer for source/drain electrodes, by epitaxial growth, in succession;
• forming a wide second recess in said contact layer;
• forming a first recess in the active layer exposed in this second recess;
• and
• regrowing selectively a gate layer having a second conductive-type conductivity in said first recess, wherein a semiconductor layer that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.

A method of manufacturing a field effect transistor which comprises the steps of:

• forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a contact layer for source/drain electrodes, by epitaxial growth, in succession;
• forming, at least, a recess in said contact layer;
• and
• regrowing selectively a gate layer having a second conductive-type conductivity in said recess;
• wherein a semiconductor layer that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.

A method of manufacturing a field effect transistor which comprises the steps of:

• forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a gate layer with second conductive-type conductivity, in succession;
• setting a gate electrode on said gate layer;
• removing portions of the gate layer other than the one beneath said gate electrode by means of etching, using the gate electrode as a mask;
• removing selectively source and drain regions of said active layer;
• regrowing ohmic contact layers for source/drain electrodes in said regions where a portion of the layer is each removed;
• and
• forming source and drain electrodes on said ohmic contact layers, respectively;
• wherein a semiconductor layer that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.

A method of manufacturing a field effect transistor which comprises the steps of:

• forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a gate layer with second conductive-type conductivity, in succession;
• patterning said gate layer into a prescribed shape;
• removing selectively source and drain regions of said active layer;
• regrowing ohmic contact layers for source/drain electrodes in said regions where a portion of the layer is each removed;
• forming a gate electrode on said gate layer;
• and
• forming source and drain electrodes on said ohmic contact layers, respectively;
• wherein a semiconductor layer that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.

A method of manufacturing a field effect transistor which comprises the steps of:

• forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a gate layer with second conductive-type conductivity, in succession;
• setting a gate electrode on said gate layer;
• removing portions of the gate layer other than the one beneath said removing portions of the gate layer other than the one beneath said gate electrode by means of etching, using the gate electrode as a mask;
• regrowing ohmic contact layers for source/drain electrodes in source and drain regions of said active layer;
• and
• forming source and drain electrodes on said ohmic contact layers, respectively;
• wherein a semiconductor layer that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.

A method of manufacturing a field effect transistor which comprises the steps of:

• forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a gate layer with second conductive-type conductivity, in succession;
• patterning said gate layer into a prescribed shape;
• regrowing ohmic contact layers for source/drain electrodes in source and drain regions of said active layer;
• forming a gate electrode on said gate layer;
• and
• forming source and drain electrodes on said ohmic contact layers, respectively;
• wherein a semiconductor layer that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.

A method of manufacturing a field effect transistor which comprises the steps of:

• forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, a channel layer, an etching stopper layer to overlie said channel layer and an ohmic contact layer for source/drain electrodes to overlie said stopper layer, by epitaxial growth, in succession;
• forming, on said ohmic contact layer, a mask layer in which an opening for a gate region is made;
• removing a portion of the ohmic contact layer that is exposed in the opening section of said mask layer so as to form a depressed section;
• and
• forming, in said formed depressed section, a first conductive-type semiconductor layer and a second conductive-type gate layer by epitaxial growth;
• wherein a semiconductor layer that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.

A method of manufacturing a field effect transistor which comprises the steps of:

• forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an etching stopper layer and an ohmic contact layer for source/drain electrodes to overlie said stopper layer, by epitaxial growth, in succession;
• forming, on said ohmic contact layer, a mask layer in which an opening for a gate region is made;
• removing a portion of the ohmic contact layer that is exposed in the opening section of said mask layer so as to form a depressed section;
• and
• forming, in said formed depressed section, a first conductive-type semiconductor layer that includes a channel layer and a second conductive-type gate layer by epitaxial growth;
• wherein a semiconductor layer that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.