Method for fabricating a capacitor in a semiconductor memory device

A method for fabricating a capacitor of a semiconductor memory device having a dielectric layer between a lower electrode and an upper electrode, said method comprising:

• after formation of a transistor having an impurity diffusion region on a semiconductor substrate, forming a first interlayer insulation layer for planarization of a top surface of the semiconductor substrate in which the transistor is formed;
• after formation of an opening on the impurity diffusion region of the transistor, forming a landing pad contacting the impurity diffusion region of the transistor;
• depositing a second interlayer insulation layer for formation of the capacitor lower electrode on the first interlayer insulation layer and the landing pad, and then forming an opening for exposing the landing pad in contact with a part of the impurity diffusion region of the transistor;
• after deposition of an insulation layer onto the top surface of the substrate, etching the insulation layer, and thereby forming a spacer having an upper surface in an inner wall of the opening;
• after deposition of a conductive layer for the capacitor lower electrode onto the top surface of the substrate on which said spacer is formed, performing a planarization process until a part of the upper surface of the spacer is exposed;
• and
• after removal of the exposed spacer, forming the dielectric layer and a conductive layer for the upper electrode of the capacitor.

A method for fabricating a capacitor of a semiconductor memory device having a dielectric layer between a lower electrode and an upper electrode, said method comprising:

• after formation of a transistor on a semiconductor substrate, forming a landing pad contacting an impurity diffusion region of the transistor;
• depositing a first interlayer insulation layer for planarization of a surface of the semiconductor substrate in which the landing pad is formed;
• after forming an opening in the first interlayer insulation layer, forming a bit line connected with a part of the impurity diffusion region of the transistor by forming a conductive material;
• depositing a second interlayer insulation layer on the semiconductor substrate in which the bit line is formed;
• after forming a contact hole which exposes a part of a surface of the landing pad by etching a part of the first and second interlayer insulation layers, filling the contact hole with a conductive material, the conductive material having at least an upper surface;
• after forming a third interlayer insulation layer on the resulting fabricated product and forming an opening in a given region of the third interlayer insulation layer so that the upper surface of the conductive material in the contact hole is exposed, forming a spacer inside the opening, the spacer having at least an upper surface;
• after deposition of a conductive layer for the capacitor lower electrode on the resulting fabricated product, performing a planarization process until a part of the upper surface of the spacer is exposed;
• and
• after removal of the partially exposed spacer, forming a conductive layer for the capacitor upper electrode and the dielectric layer.