Method of manufacturing interconnect
OwnerChien-Chih Lin, Bill Hsu +1inventors
InventorsChien-Chih Lin, Bill Hsu, Nien-Tsu Peng
Life of this patent
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Abstract
A method of manufacturing an interconnect. A wafer having an edge region and an interior region is provided. An insulating layer is formed on the wafer. An opening penetrating through the insulating layer in the interior region is formed and a portion of the insulating layer is removed to expose the surface of the wafer in the edge region, simultaneously. A conductive layer is formed on the insulating layer and the wafer exposed by the insulating layer and fills the opening. The conductive layer is patterned to form a wire in the opening.
Claims8
A method of manufacturing an interconnect on a wafer, wherein the wafer has an edge region and an interior region, the method comprising the steps of:
- forming an insulating layer on the wafer having an interior region and a edge region;
- forming an opening penetrating through the insulating layer in the interior region and removing a portion of the insulating layer to expose a surface of the wafer in the edge region, simultaneously;
- forming a conductive layer on the insulating layer and the wafer exposed by the insulating layer and filling the opening;
- and
- patterning the conductive layer to form a wire in the opening.
Dependencies are inferred from the claim text.