Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor device having a memory cell array in which non-volatile memory transistors each including a floating gate electrode and a control gate electrode coupled in capacity thereto are formed in array, said method comprising the steps of:

• sequentially depositing a gate electrode and a mask layer on a semiconductor substrate through a gate insulation film;
• forming a trench in an element isolation region by etching said gate electrode, said gate insulation film and said semiconductor substrate in sequence by anisotropic etching;
• filling said element isolation insulation film in said trench substantially flush with said mask layer, with said mask layer remaining left;
• removing at least a part of said mask layer in a layer thicknesswise direction thereof, and thereafter recessing an upper edge corner of said element isolation insulation film by isotropic etching;
• a step of removing said mask layer, and thereafter depositing a second gate electrode composing a floating gate electrode together with said first gate electrode;
• forming a slit for isolating said second gate electrode in said element isolation insulation film;
• a step of providing a control gate electrode on said second gate electrode through an inter-layer gate insulation film;
• and
• forming said floating gate electrode of each of said memory transistors by patterning said second and first gate electrodes in self-alignment with said control gate electrode.