Non-volatile memory cell having bilayered floating gate and fabricating method thereof

A method for forming a non-volatile memory cell, comprising the steps of:

• (a) forming a tunnel oxide layer on a first conductivity type semiconductor substrate;
• (b) forming first polysilicon layer lines longitudinally arranged in a bit line direction and separated from each other by a predetermined direction on the tunnel oxide layer;
• (c) forming source and drain regions by implanting second conductivity type impurity ions in the semiconductor substrate restricted by the first polysilicon layer lines;
• (d) forming first polysilicon layer patterns in the form of islands by patterning the first polysilicon layer lines;
• (e) forming buried oxide layers for filling spaces between the first polysilicon layer patterns;
• (f) forming second polysilicon layer lines longitudinally arranged in the bit line direction to be separated from each other on the buried oxide layers and the first polysilicon layer patterns so that the second polysilicon layer lines completely cover the first polysilicon layer patterns;
• (g) forming an interlayer dielectric layer on the exposed surfaces of the second polysilicon layer lines and the buried oxide layers;
• (h) forming third polysilicon layer patterns longitudinally arranged in a word line direction on the interlayer dielectric layer so that the third polysilicon layer patterns completely overlap the first polysilicon layer patterns and partially overlap the second polysilicon layer lines;
• and
• (i) sequentially removing the interlayer dielectric layer and the second polysilicon layer lines exposed by the third polysilicon layer patterns.