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US 2001/0017562 A1Published application
Flip-flop circuit
AssigneeNEC Corporation
InventorSatomi Horita
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AssigneeNEC Corporation
InventorSatomi Horita
Estimating the term…
Flip-flop circuits FF1 to FF6 are each constructed as a pair of cascade connected latch circuits 21 and 22 in an arbitrarily combination. The latch circuits L1 and L2 each comprises an input stage push-pull circuit PP and an output stage hold circuit HD as CVSL circuit. The latch circuit L1 includes an input stage having two pairs of nMOSTs 2 to 5 receiving input data DP and DN inputted thereto and connected in series each and in parallel connection of the pairs and a pair of nMOSTs 1 to 6 receiving a clock CP inputted thereto and connected to the opposite sides of the parallel connection. The output stage hold circuit HD includes a CVSI circuit having two pairs of nMOSTs 7 and 10 and a pair of pMOSTs 12 and 13 and an nMOST 11 receiving a clock CN inputted thereto. Thus obtained flip-flop (FF) circuit permits construction of a high density semiconductor integrated circuit (IC) with fast operation and low power consumption.
A flip-flop circuit comprising a pair of latch circuits each including a push-pull circuit input stage and a hold circuit output stage, the pair latch circuits being cascade connected as a master latch and a slave latch so as to be operable under control of a clock signal from a clock line.
A flip-flop circuit comprising a pair of latch circuits each including a push-pull circuit input stage and a hold circuit output stage, the pair latch circuits being cascade connected as a master latch and a slave latch so as to be operable under control of a clock signal from a clock line, the input stage of each latch circuit having two pairs of nMOS transistors or nMOSTs with push-pull data inputted thereto and connected in series/parallel connection, and the series/parallel connection being connected via an nMOST with a clock signal inputted thereto between positive supply voltage side and ground.
A flip-flop circuit comprising a pair of latch circuits each including a push-pull circuit input stage and a hold circuit output stage, the pair latch circuits being cascade connected as a master latch and a slave latch so as to be operable under control of a clock signal from a clock line, the input stage of each latch circuit having two pairs of nMOSTs, these pairs each receiving push-pull data inputted thereto, the nMOSTs in each of the pairs being connected in series between the positive supply voltage side and the ground, and a pair of clock controlled series nMOSTs each connected between the juncture of the nMOSTs in each pair and the output stage.
Dependencies are inferred from the claim text.