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US 2001/0017556 A1Published application
Frequency multiplier without spurious oscillation
AssigneeFujitsu Quantum Devices Limited
InventorsTsuneo Tokumitsu, Osamu Baba
Life of this patent
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Abstract
A damping resistance 20 is connected between the drain D of an FET 10 and a first end T3 of an output transmission line 13, and a damping resistance 21 is connected between the drain D of an FET 11 and the first end T3. The source of the FET 10 and the gate of the FET 11 are connected to a ground plane on the back surface of a substrate through a via which has a parasitic inductance when a multiplied frequency exceeds 20 GHz. The gate of the FET 10 and the source of the FET 11 receive microwaves of the same frequency and phase through an input transmission line 12.
Claims18
A frequency multiplier comprising:
- an input transmission line, receiving an incoming microwave signal;
- an output transmission line;
- a first transistor, having a first control input and a first current path, said first control input being coupled to said input transmission line, a first end of said first current path being connected to ground;
- a second transistor, having a second control input and a second current path, said second control input being connected to ground, a first end of said second current path being coupled to said input transmission line;
- a first damping resistance, connected between a second end of said first current path and said output transmission line;
- and
- a second damping resistance, connected between a second end of said second current path and said output transmission line.
4 more elements
Dependencies are inferred from the claim text.