Method of forming a buried bitline in a vertical DRAM device
AssigneeInternational Business Machines Corporation
InventorsLaertis Economikos, Hussein Ibrahim Hanafi, Thomas Safron Kanarsky, Cheruvu Suryanarayana Murthy
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Abstract
A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device is disclosed which utilizes annealing and oxidation to drive-in and pile-up the dopant atom into an outdiffused region. The anneal/oxidation which is carried out at two different temperature ranges allows for fabricating buried bitlines having the lowest resistance as possible at a maximum dopant concentration, yet being formed near the surface interface of the vertical pillars. Semiconductor memory devices containing the outdiffused buried bitline regions are also disclosed.
Claims20
A method of forming a shallow outdiffused buried bitline in a vertical semiconductor memory device comprising the steps of:
- (a) providing a structure having a dielectric layer on at least one surface of a p-type semiconducting material;
- (b) forming pillar regions in said structure provided in (a) by etching trenches in said structure;
- (c) forming a recessed liner in said trenches, wherein said recessed liner is composed of arsenic (As) or phosphorous (P) doped glass;
- (d) forming a first oxide layer over the entire structure;
- (e) annealing the structure so as to diffuse As and P into said semiconducting material and said pillar regions;
- (f) oxidizing the structure provided in (e) so as to form a second oxide layer lining said pillars of said semiconducting material and to pile-up said As or P dopants in a region beneath said second oxide layer;
- (g) removing said first oxide layer, said second oxide layer and any remaining recessed liner from said trenches;
- and
- (h) etching said semiconducting material in said trenches so as to provide separate outdiffused buried bitline regions which are formed on the pillars' sidewalls.
A vertical semiconductor memory device comprising:
- a p-type semiconducting material;
- an array of cells having pillars formed on said p-type semiconducting material, said pillars extending upward and being arranged in rows and columns, each of said pillars having an upper region doped with a n-type of impurity, a middle region which is composed of said p-type semiconducting material, and separate, lower regions outdiffused from the pillars' sidewalls which are doped with As and P, said middle region being continuous with the semiconducting material;
- and gate regions positioned adjacent to said pillars.
Dependencies are inferred from the claim text.