Method for operating non-volatile memory cells

A method of equalizing erase rates of flash cells in a memory array, the flash cells each having a floating gate with an floating gate charge value, and which floating gate charge value is intended to be set to a target initial charge value prior to an erase operation, the method comprising:

• (a) generating a flash cell conditioning signal having a predetermined magnitude and duration;
• (b) adjusting the floating gate charge value of each of such flash cells using said conditioning signal, the floating gate charge value for any such flash cell being adjusted by said conditioning signal by a charge amount proportional to the floating gate charge value;
• wherein erase rates of flash cells with floating gate charge values substantially in excess of said target initial charge value are substantially affected by said flash cell conditioning signal, while erase rates of flash cells with floating gate charge values substantially below said target initial charge values are substantially unaffected by said flash cell conditioning signal;
• and
• further wherein steps (a) and (b) are repeated until the flash cell floating gate charge values substantially converge to the target initial charge value so that all of the flash cells can then be erased at an approximately uniform erase rate by a subsequent erase operation.

A method of erasing flash memory cells in a flash memory cell array, the method including the steps of:

• (a) modifying electrical charge on floating gates of the flash memory cells by applying a partial erase signal having a magnitude and duration configured to affect substantially less electrical charge on said floating gates than that electrical charge required to place such memory cells into a filly erased state;
• and
• (b) repeating step (a) for a first number of pulses n so as to substantially equalize electrical field intensities across tunnel oxides associated with said floating gates of the flash memory cells;
• (c) performing an erase operation by applying an erase signal for a second number of pulses N (where N>>n) to place such cells in said filly erased state.

A method of erasing flash memory cells in a flash memory cell array, the method including the steps of:

• (a) modifying electrical charge on floating gates of the flash memory cells while they are in a non-erased state by applying a partial erase signal adapted to be substantially lower in intensity than a full strength erase signal;
• and
• (b) repeating step (a) if necessary for a first number of pulses n to substantially reduce threshold voltages of all of the flash memory cells to be below a target threshold voltage value;
• (c) applying an erase signal to such flash cells, which erase signal is adapted to place such cells in a fully erased state, for a second number of pulses N, where N>>n,;
• (d) determining whether such flash cells are actually in said fully erased state;
• and
• (e) if such flash cells are not in a fully erased state, performing a convergence cycle on the flash cells to adjust said threshold voltages to a fully erased state.

A method of operating flash memory cells in a flash memory cell array, the method including the steps of:

• (a) placing such flash memory cells into a programmed state;
• and
• (b) modifying electrical charge on floating gates of the flash memory cells while they are in said programmed state by applying a partial erase signal adapted to be substantially lower in intensity than a full strength erase signal;
• and
• (c) repeating step (b) for a number of pulses n so as to ensure that a threshold voltage of all of said flash memory cells is below a target threshold voltage value, and said flash memory cells have approximately equal erase rates;
• (d) applying an erase signal for a second number of pulses N (where N>>n) to such flash cells so as to place such cells in a fully erased state.

A method of making a flash memory integrated circuit, said method including the steps of:

• (a) providing an array of flash memory cells in said integrated circuit, each of said cells having a conduction threshold voltage, a control gate, a floating gate, a source and a drain;
• and
• (b) providing a control circuit coupled to said array for adjusting the threshold voltages of the cells prior to an erase operation, the control circuit being configured such that:
• i) electrical charge on floating gates of the flash memory cells is modified by applying a partial erase signal having a magnitude and duration configured to affect substantially less electrical charge on said floating gates than that electrical charge required to place such memory cells into a fully erased state;
• and
• ii) the modification of said charge during step (i) can be repeated as desired to substantially equalize electrical field intensities across tunnel oxides associated with said floating gates of the flash memory cells;
• iii) a full strength erase signal can be applied to such flash cells so as to place such cells in said fully erased state.
• wherein a probability of any cell becoming over-erased from the full strength erase signal is reduced.

A control circuit for slowing down erase speeds of fast discharge flash cells in a memory array, such fast discharge flash cells being characterized by erase speeds substantially faster than target erase speeds for flash cells in said array, the circuit comprising:

• (a) a pre-erase signal generator for generating a flash cell pre-erase signal to be applied to the flash cells;
• and
• (b) a pre-erase signal magnitude control circuit for generating a plurality of control signals, said control signals configuring a magnitude for said pre-erase signal;
• (c) a pre-erase voltage supply circuit for generating a negative voltage source;
• (d) a pre-erase voltage supply switching circuit for generating a pre-erase voltage supply signal that is based on said negative voltage source;
• (e) a pre-erase voltage supply switching control circuit configured to control gating of said pre-erase voltage supply switching circuit with a stepping signal such that said pre-erase voltage supply signal is generated as a function of said plurality of control signals and in a time sequence determined by said pre-erase signal magnitude control circuit;
• wherein said flash cell pre-erase signal is configured to remove a quantity of charge from the flash cells in preparation for an erase operation, said quantity of charge being related to an erase speed of the flash cell and further being insufficient to place such flash cells into an erased state.

A circuit for equalizing erase rates of flash cells in a memory array, the flash cells each having a floating gate with an floating gate charge value, and which floating gate charge value is intended to be set to a target initial charge value prior to an erase operation, the circuit comprising:

• (a) a flash cell controller circuit configured to generate a set of control signals for controlling a magnitude, duration and sequence associated with a flash cell conditioning signal;
• (b) a flash cell conditioning signal generator for generating said flash cell conditioning signal in response to said set of control signals;
• and
• wherein said flash cell conditioning signal is used for adjusting the floating gate charge value of each of such flash cells and operates to adjust the floating gate charge value for any such flash cell by a charge amount proportional to an original starting floating gate charge value;
• and
• further wherein erase rates of flash cells with floating gate charge values substantially in excess of said target initial charge value are substantially affected by said flash cell conditioning signal, while erase rates of flash cells with floating gate charge values substantially below said target initial charge values are substantially unaffected by said flash cell conditioning signal.