On-chip circuit and method for testing memory devices

An on-chip test circuit in an integrated circuit memory device, the memory device including a data terminal adapted to receive a data signal, and an array having a plurality of memory cells arranged in rows and columns, each memory cell storing a bit of data and having an associated address, comprising:

• a test mode terminal adapted to receive a test mode signal;
• an external clock terminal adapted to receive an external clock signal having a frequency;
• a clock multiplier circuit having an input coupled to the external clock terminal, the multiplier circuit developing an internal clock signal on an output in response to the external clock signal, the internal clock signal having a frequency greater than the frequency of the external clock signal;
• a test data storage circuit including an input, output, and terminals adapted to receive respective control signals, the test data storage circuit operable in a first mode responsive to the control signals to store bits of data applied on the input, and operable in a second mode responsive to the control signals to provide on its output the stored bits of data;
• an error detection circuit having inputs coupled respectively to the array and the output of the test data storage circuit, the error detection circuit activating an error signal on an output when the compared data is unequal;
• a switch circuit including a first terminal coupled to the data terminal, a second terminal coupled to the input of the test data storage circuit, a third terminal coupled to the array, and a fourth terminal coupled to the output of the error detection circuit, the switch circuit selectively coupling the first terminal to one of the second, third, and fourth terminals responsive to a control signal;
• and
• a test control circuit coupled to the output of the clock multiplier circuit, the test mode terminal, the array, and the control terminal of the switch circuit, the test control circuit operable responsive to the internal clock signal when the test mode signal is inactive to couple the data terminal to the array, and operable when the test mode signal is active to develop control signals to couple the data terminal to the input of the test data storage circuit, transfer data applied on the data terminal into the test data storage circuit, transfer data stored in the test data storage circuit into memory cells in the array, access the data in respective memory cells in the array and the data in the storage circuit that was initially transferred to the memory cell such that the error detection circuit compares these two bits of data, and couple the output of the error detection circuit to the data terminal so that the error signal is developed on the data terminal.

A memory device, comprising:

• an address bus;
• a control bus;
• a data bus;
• a terminal adapted to receive a test mode signal;
• an address decoder coupled to the address bus;
• a control circuit coupled to the control bus;
• a read/write circuit coupled to the data bus;
• a memory-cell array coupled to the address decoder and read/write circuit, the array having a plurality of memory cells arranged in rows and columns, each memory cell storing a bit of data;
• and
• a test circuit coupled to the data bus, including,
• a test data storage circuit including an input coupled to the data terminal and an output coupled to the memory-cell array, and terminals adapted to receive respective read test data and write test data signals, the test data storage circuit storing bits of data applied on the data terminal when the write test data signal is active, and providing on its output the bits of stored data when the read test data signal is active,
• an error detection circuit including a first input coupled to the memory-cell array and a second input coupled to the output of the test data storage circuit, the error detection circuit developing an active error signal on an output when the data on its inputs is unequal, and
• a test control circuit coupled to the terminals of the test data storage circuit, and to the test mode terminal, the test control circuit operable, when the test mode signal is active, in a first mode to activate the write test data signal and transfer data applied on the data terminal into the storage circuit, operable in a second mode to activate the read test data signal and transfer data from the storage circuit to the memory cells in the array, and operable in a third mode to activate the read test data signal and access data stored in the memory cells such that the error detection circuit compares the data stored in each memory cell to the data initially transferred to that memory cell.

A test system for detecting defects in a memory device, comprising:

• a memory device including,
• address, data and control buses to which an address decoder, read/write circuit, and control circuit are coupled, respectively,
• a terminal adapted to receive a test mode signal,
• a memory-cell array coupled to the address decoder and read/write circuit, the array having a plurality of memory cells arranged in rows and columns, each memory cell storing a bit of data, and
• a test circuit coupled to the data bus, including,
• a test data storage circuit including an input coupled to the data terminal and an output coupled to the memory-cell array, and terminals adapted to receive respective read test data and write test data signals, the test data storage circuit storing bits of data applied on the data terminal when the write test data signal is active, and providing on its output the bits of stored data when the read test data signal is active,
• an error detection circuit including a first input coupled to the memory-cell array and a second input coupled to the output of the test data storage circuit, the error detection circuit developing an active error signal on an output when the data on its inputs is unequal, and
• a test control circuit coupled to the terminals of the test data storage circuit, and to the test mode terminal, the test control circuit operable, when the test mode signal is active, in a first mode to activate the write test data signal and transfer data applied on the data terminal into the storage circuit, operable in a second mode to activate the read test data signal and transfer data from the storage circuit to the memory cells in the array, and operable in a third mode to activate the read test data signal and access data stored in the memory cells such that the error detection circuit compares the data stored in each memory cell to the data initially transferred to that memory cell;
• and
• a test device coupled to the address, data, and control buses of the memory device and to the test mode terminal, the test device activating the test mode signal to place the memory device into a test mode and thereafter transferring a predetermined test pattern of data over the data bus to the test circuit, and detecting a defect in the memory device when the error signal goes active.

A computer system, comprising:

• a data input device;
• a data output device;
• and
• computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device having a data terminal adapted to receive a data signal, and a test circuit including a memory-cell array having a plurality of memory cells arranged in rows and columns, each memory cell storing a bit of data, the test circuit including,
• a test mode terminal adapted to receive a test mode signal,
• a test data storage circuit including an input coupled to the data terminal and an output coupled to the memory-cell array, and terminals adapted to receive respective read test data and write test data signals, the test data storage circuit storing bits of data applied on the data terminal when the write test data signal is active, and providing on its output the bits of stored data when the read test data signal is active,
• an error detection circuit including a first input coupled to the memory-cell array and a second input coupled to the output of the test data storage circuit, the error detection circuit developing an active error signal on an output when the data on its inputs is unequal, and
• a test control circuit coupled to the terminals of the test data storage circuit, and to the test mode terminal, the test control circuit operable, when the test mode signal is active, in a first mode to activate the write test data signal and transfer data applied on the data terminal into the storage circuit, operable in a second mode to activate the read test data signal and transfer data from the storage circuit to the memory cells in the array, and operable in a third mode to activate the read test data signal and access data stored in the memory cells such that the error detection circuit compares the data stored in each memory cell to the data initially transferred to that memory cell.

A method for detecting defective memory cells in an array including a plurality of memory cells in an integrated circuit memory device, the memory device including data terminals adapted to receive data, the method comprising the steps of:

• placing the memory device in a test mode;
• storing in the memory device a plurality of bits of test data applied on the data terminals;
• transferring the stored test data to the memory cells;
• comparing the test data stored in each of the memory cells to the corresponding test data initially transferred to the memory cell;
• and
• detecting an error in a memory cell when the step of comparing indicates the data stored in the memory cell does not equal the test data transferred to the memory cell.

A method for testing a memory device including a memory-cell array having a plurality of memory cells, the memory device including a data terminal adapted to receive data, a clock terminal adapted to receive an external clock signal having a frequency, an internal clock node on which is developed an internal clock signal having a frequency greater than the external clock signal, the memory device further including a test data storage circuit coupled to the internal clock node which stores a plurality of bits of data, the method comprising the steps of:

• applying test data sequentially on the data terminal;
• storing the test data applied on the data terminal in the test data storage circuit at a rate determined by the external clock signal;
• transferring test data in a predetermined sequence from the test data storage circuit to respective addressed memory cells at a rate determined by the internal clock signal;
• accessing a memory cell;
• accessing the data in the storage circuit that was transferred to the accessed memory cell;
• comparing the test data stored in the accessed memory cell to the corresponding accessed data in the test data storage circuit at the rate determined by the internal clock signal;
• detecting an error in a memory cell when the step of comparing indicates the data stored in the accessed memory cell does not equal the corresponding test data in the storage circuit;
• activating an error signal on the data terminal when an error is detected;
• and
• repeating the steps of accessing a memory cell through activating an error signal for each memory cell in the memory-cell array.