US 2001/0013082 A1 · Memory paging control apparatus

Abstract

An apparatus is described for controlling data transfer operations between a memory having a plurality of addressable pages and a device operable to write data to and read data from the memory. A memory controller couples the device with the memory and includes a register for storing an open page address. The memory controller receives a read or write request from the device, together with an address corresponding with the requested page from or to which the read or write is to be performed. The memory controller includes an address comparator which compares the requested page address with the stored open page address to determine whether the requested page is already open. The memory controller then initiates the appropriate sequence of memory operations to effect the requested read or write data transfer. If a read request, the requested memory page is left open after completion of data transfer operations. If a write request, the requested memory page is closed and precharged following completion of the data transfer operations.

Claims13

Dependent claims

A computer system, comprising:

a memory operable to store data;
a device operable to read data from and write data to the memory;
and
a memory controller coupling the memory with the device and operable to apply a plurality of control signals to the memory to control data transfer operations between the device and the memory, the memory controller operable to place the memory in a first state subsequent to the device reading data from the memory, and the memory controller further operable to place the memory in a state other than the first state subsequent to the device writing data to the memory.

1 more element

In a system having a device operable to write data to and read data from a memory having a plurality of addressable memory pages, a memory controller coupling the device with the memory and adapted to receive a request type signal and a request page address, the request type signal having write and read states and the request page address corresponding with a memory page to or from which the device has requested to write or read data, respectively, the memory controller comprising:

a register operable to store a stored page address corresponding to an open memory page;
an address comparator operable to receive and compare the request page address with the stored page address and to responsively produce an address compare signal having asserted and deasserted states, the address compare signal having an asserted state when the request page address matches the stored page address;
and
a control state machine operable to receive the request type and the address compare signals and to responsively apply a plurality of control signals to the memory controlling the operation thereof, the control state machine responding to the address compare signal of the deasserted state to open the memory page corresponding with the request page address, the control state machine responding to the request type signal of the read state to initiate reading data from the memory page corresponding with the request page address, and the control state machine further responding to the request type signal of the read state to leave open the memory page corresponding with the request page address.

1 more element

A computer system, comprising:

a memory operable to store data in a plurality of pages, each being identified by a corresponding page address;
a device operable to request read and write data transfer operations with the memory, the device operable to provide a request type signal having read and write states to request the read and write data transfer operations, respectively, the device further operable to provide a request page address corresponding to a requested page in the memory from or to which data is to be transferred;
and
a memory controller coupling the memory with the device and controlling data transfer operations therebetween, the memory controller comprising:
a register operable to store a stored page address corresponding to an open page in the memory;
an address comparator operable to receive and compare the request page address with the stored page address, the address comparator producing an address compare signal having asserted and deasserted states, the address compare signal having an asserted state when the request page address matches the stored page address;
and
a control state machine operable to receive the request type and the address compare signals and to responsively apply a plurality of control signals to the memory to control the operations thereof, the control state machine responding to the address compare signal of the deasserted state to open the requested page, the control state machine responding to the request type signal of the read state to initiate the read data transfer operation with the requested page, to leave open the requested page upon completion of the read data transfer operation, and to modify the stored page address to correspond with the request page address.

5 more elements

Dependencies are inferred from the claim text.

Memory paging control apparatus

Life of this patent

Memory paging control apparatus

Life of this patent

Abstract

Claims13