Mos transistor having self-aligned well bias area and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorKim Gyu-chul
Life of this patent
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Abstract
A MOS transistor having a self-aligned well bias area and a method of fabricating the same provide for efficient application of well bias in a highly integrated semiconductor substrate without causing latch-up. The well bias area is formed at a trench, which is formed by etching a semiconductor substrate in a manner of self-alignment, so that well bias can be efficiently applied to the MOS transistor achieving reduction of the area of a chip without degradation of electrical characteristics.
Claims15
A MOS transistor having a self-aligned well bias region, the MOS transistor comprising:
- a semiconductor substrate on which a well of a first conductivity type is formed;
- at least two gate patterns, each of which includes a gate oxide film, a gate electrode and a capping layer which are sequentially stacked on the semiconductor substrate, and a gate spacer formed on the sidewalls of the gate electrode and the capping layer;
- source/drain regions doped with second conductivity type impurities, the source/drain regions formed in the surface of the semiconductor substrate adjacent to the gate patterns;
- a trench formed between the gate patterns by etching the semiconductor substrate in a manner of self-alignment using the gate spacer;
- a well bias area formed at the side of the lower portion and the bottom of the trench;
- and
- a contact filling the self-aligned trench.
A method of fabricating a MOS transistor having a self-aligned well bias region, the method comprising the steps of:
- sequentially stacking a gate oxide film, a gate electrode and a capping layer on a semiconductor substrate having a first conductivity type well;
- patterning the capping layer and the gate electrode;
- ion-implanting a low concentration of impurities of a second conductivity type in the semiconductor substrate using the patterned gate electrode as an ion-implantation mask, thereby forming an LDD region;
- depositing an insulating film for a spacer on the entire surface of the semiconductor substrate with the LDD region and anisotropically etching the resultant structure, thereby forming a gate spacer;
- implanting second conductivity type impurities in the semiconductor substrate using a gate pattern with the gate spacer as an ion-implantation mask, thereby forming a high concentration impurity region;
- forming a photoresist pattern on the resultant structure such that the high concentration impurity region between gate patterns is exposed;
- etching the semiconductor substrate in a self-aligning manner using the capping layer and the gate spacer, thereby forming a trench;
- ion-implanting first conductivity type impurities in a side of the lower portion and the bottom of the trench, thereby forming a well bias area;
- and
- removing the photoresist pattern and filling the trench with a conductive material, thereby forming a contact.
Dependencies are inferred from the claim text.