Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry

A method of forming a pair of field effect transistors comprising:

• forming a pair of active areas over a substrate, one of the active areas having a width less than one micron;
• forming a gate line over both active areas to provide a pair of transistors having different threshold voltages, the transistors being provided with the different threshold voltages without using a separate channel implant for either transistor;
• and
• wherein the transistor with the lower of the threshold voltages corresponds to the active area having the width less than one micron.

A semiconductor processing method of forming dynamic random access memory circuitry comprising:

• providing a substrate having a memory array area over which memory circuitry is to be formed, and a peripheral area over which peripheral circuitry is to be formed;
• forming a plurality of shallow trench isolation regions received within the peripheral area of the substrate, the shallow trench isolation regions being formed to define a plurality of active areas having widths within the substrate, some of the widths being no greater than about one micron, at least two of the widths being different;
• and
• forming a conductive line over respective active areas to provide individual transistor gates, the transistors corresponding to the active areas having the different widths having different threshold voltages.

Dynamic random access memory circuitry comprising:

• a substrate having a memory array area for supporting memory circuitry and a peripheral area for supporting peripheral circuitry;
• a plurality of active areas within the peripheral area having widths defined by shallow trench isolation regions of no greater than about one micron, at least some of the widths being different;
• and
• conductive lines disposed over the plurality of active areas to provide individual transistors, those transistors whose widths are different having different threshold voltages from one another.

A transistor assembly comprising:

• an active area;
• a plurality of spaced-apart shallow trench isolation regions received by the active area and defining active sub-areas therebetween, individual active sub-areas having respective widths, at least one of the widths being no greater than about one micron and at least one other sub-area having a width which is different from the one width;
• and
• a gate line extending over the one and the other sub-area and defining, in part, separate transistors, wherein the separate transistors have different threshold voltages.

A transistor assembly comprising:

• an active area;
• a plurality of spaced-apart shallow trench isolation regions received by the active area and defining active sub-areas therebetween, individual active sub-areas having respective widths, at least one of the widths being no greater than about one micron and at least one other sub-area having a width which is less than the one width;
• and
• a gate line extending over the one and the other sub-area and defining, in part, separate transistors, wherein the separate transistors have different threshold voltages, wherein said gate line comprises a common gate line which extends over a plurality of the active sub-areas defining a plurality of transistors, each active sub-area width of an associated transistor being no greater than about one micron and said plurality of transistors being joined in a parallel configuration to provide a pull down circuit coupled to a common node.