Synchronous semiconductor memory device

A synchronous semiconductor memory device comprising:

• a memory cell array comprising a plurality of memory cells for storing data items;
• first and second sense amplifiers connected in parallel to one output terminal for amplifying said data items stored in said plurality of memory cells;
• a selector element selectively outputting said data items as output from said first and second sense amplifiers;
• and
• a first delay circuit for displacing a time point at which said second sense amplifier is activated from a time point at which said second sense amplifier is activated,
• said first and second sense amplifiers being controlled to maintain output data for a time period no shorter than a half of a cycle time of said semiconductor memory device.

A synchronous semiconductor memory device comprising:

• a memory cell array comprising a plurality of memory cells for storing data items;
• a row selection circuit receiving a row address signal and selecting a row of said memory cell array;
• a column selection circuit for receiving a column address signal and simultaneously selecting a plurality of columns of said memory cell array;
• a plurality of sense amplifiers for amplifying a plurality of data items which are selected by said row selection circuit and said column selection circuit and outputted to a plurality of data lines;
• and
• a selector element for sequentially outputting said data items which are amplified by said plurality of sense amplifiers in a time-interleaved manner,
• wherein said plurality of sense amplifiers are activated.

A method of operating a synchronous semiconductor memory device comprising the steps of:

• storing data items in a memory cell array comprising a plurality of memory cells;
• receiving a row address signal and selecting a row of said memory cell array;
• receiving a column address signal and simultaneously selecting first and second columns of said memory cell array;
• amplifying first and second data items, respectively, and outputting said first and second data items to first and second data lines;
• and
• sequentially outputting said amplified first and second data items in a time-interleaved manner, said second data item being amplified after said first data item is amplified.

A method of operating a synchronous semiconductor memory device comprising the steps of:

• storing data items in a plurality of memory cells in a memory cell array;
• amplifying said data items through first and second sense amplifiers connected in parallel to one output terminal;
• selectively outputting said data items as output from said first and second sense amplifiers;
• and
• displacing a time point at which said first sense amplifier is amplified from a time point at which said second sense amplifier is activated, and
• controlling said first and second sense amplifiers to maintain output data for a time period no shorter than a half of a cycle time of said semiconductor memory device.

A method of operating a synchronous semiconductor memory device comprising the steps of:

• storing data items in a memory cell array comprising a plurality of memory cells;
• selecting a row of said memory cell array;
• simultaneously selecting a plurality of columns of said memory cell array;
• amplifying a plurality of said data items, selected in said selecting steps, with a plurality of sense amplifiers;
• and
• sequentially outputting said amplified data items in time-interleaved manner,
• wherein said plurality of sense amplifiers are activated sequentially.