Method and apparatus for supplying regulated power to memory device components

A memory device, comprising:

• at least one array of memory cells adapted to store data at a location determined by a row address and a column address;
• a row address circuit adapted to receive and decode the row address, and to select a row of memory cells corresponding to the row address responsive to a first command signal;
• a column address circuit adapted to receive data from or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second command signal;
• a data path circuit adapted to couple data between an external terminal and the column address circuit responsive to a third command signal;
• a charge pump constructed to generate a pumped voltage to supply power to at least part of either the at least one array of memory cells or the data path;
• a first regulator circuit adapted to receive an external supply voltage and to generate a first regulated output voltage as a first function of the external supply voltage, the first regulated output voltage being used to supply power to the at least one array of memory cells;
• and
• a second regulator circuit adapted to receive the external supply voltage and to generate a second regulated output voltage as a second function of the external supply voltage that is different from the first function, the second regulated output voltage being used to supply power to the charge pump.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a memory device coupled to the processor bus, the memory device comprising:
• at least one array of memory cells adapted to store data at a location determined by a row address and a column address;
• a row address circuit adapted to receive and decode the row address, and to select a row of memory cells corresponding to the row address responsive to a first command signal;
• a column address circuit adapted to receive data from or apply data to one of the memory cells in the selected row corresponding to the column address responsive to a second command signal;
• a data path circuit adapted to couple data between an external terminal and the column address circuit responsive to a third command signal;
• a charge pump constructed to generate a pumped voltage to supply power to at least part of either the at least one array of memory cells or the data path;
• a first regulator circuit adapted to receive an external supply voltage and to generate a first regulated output voltage as a first function of the external supply voltage, the first regulated output voltage being used to supply power to the at least one array of memory cells;
• and
• a second regulator circuit adapted to receive the external supply voltage and to generate a second regulated output voltage as a second function of the external supply voltage that is different from the first function, the second regulated output voltage being used to supply power to the charge pump.

A method of powering and testing an array of memory cells and a charge pump fabricated in a common integrated circuit that is powered by an external supply voltage, the method comprising:

• supplying power to at least a portion of the array at a first voltage when the external supply voltage has a magnitude that is less than a predetermined voltage;
• supplying power to at least a portion of the array at a voltage having a magnitude that is greater than the magnitude of the first voltage when the external supply voltage has a magnitude that is greater than the predetermined voltage;
• supplying power to the charge pump at a second voltage when the external supply voltage has a magnitude that is less than the predetermined voltage;
• and
• supplying power to the charge pump at substantially the second voltage when the external supply voltage has a magnitude that is greater than the predetermined voltage.