Method for testing semiconductor wafers

An apparatus for testing a semiconductor wafer comprising:

• a base;
• an interconnect mounted to the base comprising a substrate and a contact member formed thereon for establishing electrical communication with a contact location on the wafer;
• a cover attachable to the base;
• a compressible spring member placed between the cover and the wafer for biasing the wafer against the interconnect;
• an electrical connector formed on the base;
• and
• an electrical path formed between the contact member and the electrical connector.

An apparatus for testing a semiconductor wafer comprising:

• a base comprising a conductor and an electrical connector;
• a cover attachable to the base;
• an interconnect formed on the base comprising a substrate and a contact member configured to electrically contact a contact location on the die;
• an electrical path formed between the contact member on the interconnect and the conductor on the base;
• and
• a compressible spring member placed between the cover and base to press the wafer against the interconnect.

An apparatus for testing a semiconductor wafer comprising:

• a base;
• a cover attachable to the base;
• an interconnect placed between the base and cover comprising a contact member configured to electrically contact a contact location on the wafer;
• said interconnect including a conductor in electrical communication with the contact member and an electrical connector configured for direct electrical connection with a testing apparatus;
• and
• an elastomeric spring member configured for placement between the cover and base to bias the interconnect and wafer together.

An apparatus for testing a semiconductor wafer comprising:

• a base;
• a plurality of contact members formed on the base comprising indentations and conductive layers configured to establish temporary electrical communication with a plurality of bumped contact locations on the wafer;
• a plurality of conductors formed on the base in electrical communication with the conductive layers;
• and
• a plurality of terminal contact formed on the base in electrical communication with the conductors configured for electrical connection to test circuitry.

An apparatus for testing a semiconductor wafer comprising:

• a base comprising photosensitive glass;
• a contact member formed on the base configured to establish temporary electrical communication with a contact location on the wafer;
• and
• an electrical connector formed on the base in electrical communication with the contact member configured to electrically connect to test circuitry.

An apparatus for testing a semiconductor wafer comprising:

• a base;
• a plurality of contact members formed on the base configured to establish temporary electrical communication with a plurality of contact locations on the wafer;
• a plurality of multi level conductors formed on the base in electrical communication with the contact members;
• and
• an electrical connector formed on the base in electrical communication with the contact member configured to electrically connect to test circuitry.

A system for testing a semiconductor wafer comprising:

• a wafer carrier comprising a base for retaining the wafer, a cover attachable to the base, an interconnect comprising a contact member configured to establish electrical communication with a contact location on the wafer, and a compressible spring member configured to bias the wafer against the interconnect;
• a testing apparatus operable with the carrier comprising test circuitry configured to apply test signals to the wafer;
• and
• an electrical path formed between the interconnect and the test circuitry.

A system for testing a semiconductor wafer comprising:

• a base comprising a conductor formed thereon in electrical communication with a first electrical connector;
• an interconnect formed on the base comprising a contact member in electrical communication with the conductor and configured to establish electrical communication with a contact location on the wafer;
• a cover attachable to the base;
• a compressible spring member placed between the cover and the base to bias the wafer against the base;
• and
• a testing apparatus comprising test circuitry in electrical communication with a second electrical connector configured to electrically connect with the first electrical connector.

A method for testing a semiconductor wafer comprising:

• providing a wafer carrier comprising a base for retaining the wafer, an interconnect having a contact member for establishing temporary electrical communication with the wafer, and a compressible spring member for biasing the wafer against the interconnect;
• aligning the contact member on the interconnect with the contact location on the wafer;
• placing the wafer and interconnect in contact;
• biasing the wafer and interconnect together using the spring member;
• and
• applying test signals through the interconnect to the wafer.

A method for testing a semiconductor wafer comprising:

• providing a wafer carrier for retaining the wafer;
• providing an interconnect for the wafer carrier comprising a substrate and a contact member configured to electrically contact a contact location on the wafer;
• optically aligning the contact member on the interconnect and contact location on the wafer;
• biasing the contact member against the contact location with a compressible spring member;
• and
• applying test signals through the contact member to the contact location.

A method for testing a semiconductor wafer comprising:

• providing a base for retaining the wafer comprising an electrical connector;
• forming a contact member on the base configured to electrically contact a contact location on the wafer;
• biasing the wafer against the base using a compressible spring member;
• forming an electrical path between the contact member and electrical connector;
• providing a testing apparatus comprising test circuitry;
• placing the electrical connector in electrical communication with the test circuitry;
• and
• applying test signals to the wafer.