Method and a circuit for improving the effectiveness of ESD protection in circuit structures formed in a semiconductor
AssigneeSTMicroelectronics S.r.l.
InventorsPaolo Colombo, Emilio Camerlenghi
Life of this patent
Estimating the term…
Abstract
A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate. Advantageously, the transistor can be fully isolated from the substrate by first and second N wells which extend from the surface of the epitaxial layer down to and in contact with the buried well.
Claims20
A method for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate, the method comprising overlaying the semiconductor substrate with an epitaxial layer, realizing at least one ESD protection lateral bipolar transistor in a surface of the epitaxial layer, and isolating the transistor from the substrate by providing a buried well under said transistor.
An ESD-protected circuit structure, comprising a semiconductor substrate overlaid with an epitaxial layer, at least one ESD protection lateral bipolar transistor realized in a surface of the epitaxial layer, and a buried well under said transistor for isolation of the transistor from the substrate.
An ESD-protected circuit structure, comprising:
- a semiconductor substrate having a first conductivity type;
- a lateral bipolar transistor;
- and
- a buried well having a second conductivity type opposite to the first conductivity type, the buried well being positioned below the transistor to separate the transistor from the substrate.
Dependencies are inferred from the claim text.