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AssigneeNEC Corporation
InventorKazuki Shigeta
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In evaluating the location of a failure in a logic circuit including gates defined in a hierarchical manner, the present invention discloses a system capable of evaluating the location of a failure by referring to the circuitry of a gate described by a basic gate without creating any special databases that are dedicated to evaluating the location of a failure. In this system, expected value setting device obtains an expected value of a target gate inside the logic circuit by an IF-THEN operation in an output direction, logical state evaluating device obtains a logical state of the target gate inside the logic circuit by an IF-THEN operation in an input/output direction, and a failure propagation path inside the target gate is obtained by comparing the expected value with the logical state. Furthermore, temporary decided line retrieving device retrieves an input terminal of the target gate, a temporary logical value being set thereon, by referring to the circuitry of the target gate recorded in a logic circuitry storage unit, and the expected value and the logical state inside the target gate recorded in a logical state storage unit, and then related failure terminal setting device obtains a related failure terminal in the input/output terminal of the target gate by referring to the circuitry of the target gate recorded in the logic circuitry storage unit, and the expected value and the logical state inside the target gate recorded in the logical state storage unit, when no temporary decided lines are detected, and the target gate is determined to be an established gate.
A failure location evaluating system for evaluating the location of a failure inside a logic circuit by tracing a failure propagation path from a failure terminal, comprising:
A failure location evaluating system for evaluating the location of a failure inside a logic circuit by tracing a failure propagation path from a failure terminal, comprising:
A failure location evaluating system for evaluating the location of a failure inside a logic circuit by tracing a failure propagation path from a failure terminal, comprising:
A failure location evaluating method for evaluating the location of a failure inside a logic circuit by tracing a failure propagation path from a failure terminal, comprising the steps of:
A failure location evaluating method for evaluating the location of a failure inside a logic circuit by tracing a failure propagation path from a failure terminal, comprising the steps of:
A failure location evaluating method for evaluating the location of a failure inside a logic circuit by tracing a failure propagation path from a failure terminal, comprising the steps of:
A machine-readable recording medium in a failure location evaluating system adapted to evaluate the location of a failure inside a logic circuit by tracing a failure propagation path from a failure terminal, said recording medium comprising:
A machine-readable recording medium in a failure location evaluating system adapted to evaluate the location of a failure inside a logic circuit by tracing a failure propagation path from a failure terminal, said recording medium comprising:
A machine-readable recording medium in a failure location evaluating system adapted to evaluate the location of a failure inside a logic circuit by tracing a failure propagation path from a failure terminal, said recording medium comprising:
A device for evaluating the location of a failure, comprising:
A device for evaluating the location of a failure, comprising:
A device for evaluating the location of a failure, comprising:
Dependencies are inferred from the claim text.