Dynamic memory clock control system and method

A memory clock control system for facilitating multiple memory access requests comprising:

• means for detecting memory access request data for a plurality of memory access channels to determine desired memory access by determining a duration of non-access of memory on a per access channel basis;
• a variable memory clock;
• memory containing predetermined clock rate control data for controlling the variable memory clock and
• means, operatively coupled to the detecting means, the memory and the variable memory clock, for adaptively varying the memory clock in response to determining the desired memory usage from the plurality of memory access channels, including means for generating a variable memory clock control signal in response to an amount of desired memory access wherein the means for adaptively varying decreases the memory clock speed to reduce power consumption in response to a detection of reduced memory access usage by the means for detecting and increasing the memory clock speed in response to a detection of an increase in memory access usage.