Method for preventing electrostatic discharge in an integrated circuit
AssigneeWinbond Electronics Corp.
InventorTa-Lee Yu
Life of this patent
Estimating the term…
Abstract
An integrated circuit package includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin. The size of the non-wired pin is minimized, or the non-wired pin is eliminated, in order to increase the lead pin spacing. The increase in lead pin spacing prevents electrostatic discharge failure in an integrated circuit package due to electrostatic stressing of the non-wired pin.
Claims13
A method for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin, the electrostatic discharge failure being due to electrostatic discharge stressing of the non-wired pin, said method comprising:
- minimizing the at least one non-wired pin in a lead frame in order to increase pin spacing of wired pins adjacent the non-wired pin.
A method for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin, the electrostatic discharge failure being due to electrostatic discharge stressing of the non-wired pin, said method comprising:
- removing the at least one non-wired pin in a lead frame.
A lead frame for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip, said lead frame comprising:
- a plurality of wired pins;
- and
- at least one non-wired pin formed such that no more than a tip thereof at an outermost portion remains.
A chip carrier for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip, said chip carrier comprising:
- a plurality of wired traces;
- and
- at least one non-wired trace formed such that no more than a tip at an outermost portion remains.
A method for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip mounted on a chip carrier, a plurality of wired traces and at least one non-wired trace, the electrostatic discharge being due to electrostatic discharge stressing of the non-wired trace, comprising:
- minimizing the at least one non-wired trace in order to increase spacing of wired traces adjacent the non-wired trace.
A method for preventing electrostatic discharge failure in an integrated circuit package which includes a semiconductor chip mounted on a chip carrier, a plurality of wired traces and at least one non-wired trace, the electrostatic discharge being due to electrostatic discharge stressing of the non-wired trace, comprising:
- providing the chip carrier without the at least one non-wired trace.
Dependencies are inferred from the claim text.