Wafer-level packaging structure and method for preparing same
AssigneeSJ Semiconductor(Jiangyin) Corporation
InventorsYenheng Chen, Chengchung Lin
Life of this patent
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Abstract
A wafer-level packaging structure and a method for preparing the same are provided, the wafer-level packaging structure includes at least a molding layer and a 3D IPD structure fabricated in the molding layer. The wafer-level packaging structure of the present disclosure can integrate various electronic chips and components such as millimeter wave antenna/capacitor/inductor/electric crystal/GPU/PMU/DDR/flash memory/filter, etc., with higher flexibility and wider compatibility, thus reducing package size and package cost.
Claims13
A wafer-level packaging structure, comprising a molding layer, and a 3D IPD (Integrated Passive Devices) structure fabricated in the molding layer, wherein the molding layer includes a first surface and a second surface opposite to the first surface;
- wherein the 3D IPD structure comprises one or more of a 3D inductive IPD structure, a 3D capacitive IPD structure, and a 3D resistive IPD structure;
- and
- wherein the 3D inductive IPD structure comprises:
- first metal solder pads, formed inside the molding layer and extending inwards from the first surface of the molding layer;
- metal pillars, formed inside the molding layer and located over ends of the first metal solder pads;
- and
- second metal solder pads, formed on the molding layer and extending outwards from the second surface of the molding layer, wherein the second metal solder pads connect the metal pillars in series, with each of the second metal solder pads connecting two of the metal pillars that are respectively located over two adjacent first metal solder pads, and forming the 3D inductive IPD structure.
A method for preparing a wafer-level packaging structure, including:
- preparing a molding layer;
- and
- forming a 3D IPD (Integrated Passive Devices) structure inside the molding layer, wherein the 3D IPD structure comprises one or more of a 3D inductive IPD structure, a 3D capacitive IPD structure, and a 3D resistive IPD structure;
- wherein forming the 3D inductive IPD structure inside the molding layer comprises:
- providing a substrate having a release layer, forming first metal solder pads on a surface of the release layer;
- forming metal pillars over ends of the first metal solder pads;
- forming a molding layer over the release layer to cover the metal pillars and the first metal solder pads, and thinning the molding layer and the metal pillars;
- forming second metal solder pads over the molding layer, wherein the second metal solder pads connect the metal pillars in series, with each of the second metal solder pads connecting two of the metal pillars that are respectively located over two adjacent first metal solder pads;
- and
- removing the release layer to disengage the substrate, thereby forming the 3D inductive IPD structure.
A method for preparing a wafer-level packaging structure, including:
- preparing a molding layer;
- and
- forming a 3D IPD (Integrated Passive Devices) structure inside the molding layer, wherein the 3D IPD structure comprises one or more of a 3D inductive IPD structure, a 3D capacitive IPD structure, and a 3D resistive IPD structure;
- wherein forming the 3D capacitive IPD structure inside the molding layer comprises:
- providing a substrate having a release layer, forming a molding layer on a surface of the release layer;
- etching the molding layer to form at least one pair of parallel openings exposing the release layer;
- filling the openings with metal materials to form at least one pair of metal layers are spaced apart and parallel to each other, wherein said pair of metal layers are perpendicular to one of the first and second surfaces of the molding layer;
- and
- removing the release layer to disengage the substrate, thereby forming the 3D capacitive IPD structure.
Dependencies are inferred from the claim text.