Semiconductor package and fabrication method thereof

A semiconductor package, comprising:

• a re-distribution layer (RDL) interposer having a first surface and a second surface opposite to the first surface;
• a plurality of fanout pads disposed on the second surface of the RDL interposer;
• a plurality of peripheral pads disposed on the second surface and arranged along a perimeter of the RDL interposer;
• a first semiconductor die disposed on the first surface of the RDL interposer and electrically connected to the plurality of fanout pads;
• a molding compound encapsulating the first semiconductor die and the first surface of the RDL interposer, wherein a top surface of the molding compound is coplanar with a rear surface of the first semiconductor die;
• a plurality of through mold vias disposed in the molding compound around the first semiconductor die, wherein the plurality of through mold vias exposes the plurality of peripheral pads, respectively;
• a plurality of peripheral solder bumps disposed within the plurality of through mold vias and placed directly on the plurality of peripheral pads, respectively;
• a plurality of through silicon via (TSV) pads disposed on the rear surface of the first semiconductor die;
• and
• a second semiconductor die bonded to the plurality of TSV pads of the first semiconductor die and bonded to the plurality of peripheral solder bumps within the plurality of through mold vias, wherein the second semiconductor die is bonded to the plurality of TSV pads of the first semiconductor die through a plurality of first connecting elements, wherein the second semiconductor die is bonded to the plurality of peripheral solder bumps within the plurality of through mold vias through a plurality of second connecting elements having a diameter greater than a diameter of each of the plurality of first connecting elements.