Semiconductor package including crack prevention layer

A semiconductor package comprising:

• a first wiring structure including a plurality of first redistribution patterns and a plurality of first redistribution insulating layers surrounding the plurality of first redistribution patterns;
• a second wiring structure on the first wiring structure, the second wiring structure including a plurality of second redistribution patterns, a plurality of second redistribution insulating layers surrounding the plurality of second redistribution patterns, a crack prevention layer, and a plurality of upper surface connection pad layers;
• a semiconductor chip between the first wiring structure and the second wiring structure;
• and
• an expanded structure that electrically connects the plurality of first redistribution patterns with the plurality of second redistribution patterns and surrounds the semiconductor chip, wherein
• the plurality of second redistribution insulating layers include a first insulating layer, a second insulating layer, and a third insulating layer stacked on the semiconductor chip and the expanded structure,
• the plurality of second redistribution patterns include a first wiring layer on the first insulating layer and covered by the second insulating layer, and a second wiring layer on the second insulating layer and the crack prevention layer,
• the second wiring layer is partially covered by the third insulating layer,
• the second wiring layer includes a plurality of pad portions and a plurality of line portions extending from the plurality of pad portions,
• the plurality of upper surface connection pad layers are on the plurality of pad portions, such that the plurality of pad portions and the plurality of upper surface connection pad layers form a plurality of upper surface connection pads,
• the crack prevention layer overlaps at least some of the plurality of pad portions in a vertical direction and covers at least a portion of the second insulating layer such that the crack prevention layer is spaced apart from the first wiring layer in the vertical direction with a portion of the second insulating layer therebetween in the vertical direction, wherein
• an edge region of the semiconductor package surrounds a central region of the semiconductor package in a plan view.

A semiconductor package comprising:

• a lower package including
• a first wiring structure including a plurality of first redistribution patterns and a plurality of first redistribution insulating layers surrounding the plurality of first redistribution patterns,
• a second wiring structure on the first wiring structure, the second wiring structure including a plurality of second redistribution patterns, a plurality of second redistribution insulating layers surrounding the plurality of second redistribution patterns, a crack prevention layer, and a plurality of upper surface connection pad layers,
• a semiconductor chip between the first wiring structure and the second wiring structure, and
• an expanded structure that electrically connects the plurality of first redistribution patterns with the plurality of second redistribution patterns and surrounds the semiconductor chip;
• an upper package on the lower package, the upper package including an auxiliary semiconductor chip;
• and
• a plurality of package connection terminals attached to the plurality of upper surface connection pad layers, the plurality of package connection terminals electrically connecting the lower package with the upper package, wherein
• the plurality of second redistribution insulating layers include a first insulating layer, a second insulating layer, and a third insulating layer stacked on the semiconductor chip and the expanded structure,
• the plurality of second redistribution patterns include a first wiring layer on the first insulating layer and covered by the second insulating layer, and a second wiring layer on the second insulating layer and the crack prevention layer,
• the second wiring layer is partially covered by the third insulating layer,
• the second wiring layer includes a plurality of pad portions and a plurality of line portions extending from the plurality of pad portions,
• the plurality of upper surface connection pad layers are on the plurality of pad portions, such that the plurality of pad portions and the plurality of upper surface connection pad layers form a plurality of upper surface connection pads, and
• the crack prevention layer overlaps at least some of the plurality of pad portions in a vertical direction and covers at least a portion of the second insulating layer such that the crack prevention layer is spaced apart from the first wiring layer in the vertical direction with a portion of the second insulating layer therebetween in the vertical direction.