Package substrate with embedded dies in buildup layers

A package substrate, comprising:

• a core;
• buildup layers on either side of the core;
• an IC die embedded in one of the buildup layers;
• and
• an underfill material,
• wherein:
• each buildup layer comprises a plurality of layers of conductive traces in an organic dielectric material,
• a subset of the conductive traces between a surface of the package substrate and the core comprises bond pads,
• the IC die is coupled with the bond pads by solder, and
• the underfill material is between the IC die and the bond pads.

A microelectronic assembly, comprising:

• a package substrate including a first integrated circuit (IC) die embedded therein;
• and
• a second IC die coupled with the package substrate and conductively coupled with the first IC die by conductive vias in the package substrate,
• wherein:
• the package substrate has a first side and an opposing second side,
• the second IC die is coupled with the first side of the package substrate,
• the second IC die comprises an interposer attached to a third IC die on a side of the interposer opposite to the package substrate,
• the first IC die is between the first side of the package substrate and the second side of the package substrate,
• the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material,
• the first IC die is surrounded by the organic dielectric material of the package substrate, and
• the conductive vias are in the organic dielectric material between the first IC die and the first side of the package substrate.