Split metallization layers in multichip devices

A multichip system, comprising:

• a plurality of first intradevice metallization layers coupled to a substrate, wherein one of the plurality of first intradevice metallization layers is coupled to a power supply through the substrate;
• an inorganic dielectric material over the first intradevice metallization layers;
• a first die adjacent the inorganic dielectric material and coupled to one of the plurality of first intradevice metallization layers, wherein the first die is within an area of the first intradevice metallization layers;
• a second die hybrid bonded to the first die and coupled to one of the first intradevice metallization layers by one or more first vias extending through the inorganic dielectric material within the area of the first intradevice metallization layers;
• and
• a plurality of second intradevice metallization layers hybrid bonded to, and over, the second die, wherein one of the second intradevice metallization layers is further coupled to at least one of:
• a plurality of interconnect interfaces on a side of the second intradevice metallization layers opposite the second die;
• or
• the first die by one or more second vias extending through the inorganic dielectric material within an area of the second intradevice metallization layers.